summaryrefslogtreecommitdiffstats
path: root/host/lib/usrp
Commit message (Expand)AuthorAgeFilesLines
* dsp: clear register now overlaps with numchan register.Josh Blum2012-04-091-4/+2
* usrp: fix set_clock_config typo for external and mimo clock refJosh Blum2012-04-061-2/+2
* usrp1: stop threads in deconstructorJosh Blum2012-03-293-4/+10
* dbsrx: limit the USRP1 + DBSRX GPIO clock rate to 4MHzJosh Blum2012-03-261-1/+8
* usrp2: possible fix for invalid broadcast repliesJosh Blum2012-03-261-3/+17
* usrp: fix for rx_frontend_core_200 dc offsetJosh Blum2012-03-231-3/+4
* usrp: fix typo for user setting regJosh Blum2012-03-211-1/+1
* Disabling the SBX mixer and baseband amp causes griefJason Abele2012-03-161-1/+1
* B100: enable_gpif(0) disables FIFO output clock on FX2. this prevents the "st...Nick Foster2012-03-161-2/+2
* usrp: fix from "rev iq correction"Josh Blum2012-03-163-6/+6
* n2x0: adjustment for phase delay over mimo cableJosh Blum2012-03-141-1/+1
* uhd: rev iq correction numbers formatJosh Blum2012-03-143-47/+10
* usrp: fix wildcard set for time/clock sourceJosh Blum2012-03-121-2/+2
* uhd: added fullscale option stream argJosh Blum2012-03-112-0/+4
* Make DBSRX* set default bandwidth based on codec rateJason Abele2012-03-112-2/+7
* Fix RSSI measurementJason Abele2012-03-112-18/+4
* usrp1: fix for cordic init, cant do it that way on txJosh Blum2012-02-291-3/+0
* usrp2: device locking tweaksJosh Blum2012-02-291-9/+6
* usrp: reset cordics on init after tick rate updateJosh Blum2012-02-284-0/+33
* uhd: fixed some compile warnings for msvcJosh Blum2012-02-282-2/+2
* usrp1: fix to use the db connection type to determine DAC signJosh Blum2012-02-241-2/+10
* usrp1: fix advertised samples per packet in send streamerJosh Blum2012-02-211-1/+2
* usrp2: some tweaks to the device locking logicJosh Blum2012-02-201-6/+9
* usrp2: added retry logic to control packetsJosh Blum2012-02-201-2/+32
* Merge branch 'next'Josh Blum2012-02-1731-223/+502
|\
| * dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-152-5/+8
| * uhd: added async md user payload and common utilsJosh Blum2012-02-144-45/+88
| * b100: use frame boundary to calculate frame sizeJosh Blum2012-02-141-2/+2
| * b100: reset/reenumerate fx2 for bad endpoint stateJosh Blum2012-02-143-0/+31
| * b100: added transport flushes and moved around reset codeJosh Blum2012-02-143-13/+7
| * b100/usrp1: various tweaks for compiler warns and valgrindJosh Blum2012-02-094-9/+10
| * uhd: various tweaks for compiler warns and valgrindJosh Blum2012-02-096-11/+15
| * B100: Firmware reset tweaks.Nick Foster2012-02-091-1/+1
| * dsp rework: implement 64 bit ticks, no secondsJosh Blum2012-02-0613-61/+63
| * B100: use FPGA external reset on initNick Foster2012-02-062-0/+7
| * b100/e100: unify rx/tx fifo clears into oneJosh Blum2012-02-044-14/+8
| * b100: delete some unused registers from mapJosh Blum2012-02-042-7/+0
| * dsp rework: move setting address of format registerJosh Blum2012-02-022-6/+4
| * dsp rework: work on usb wrapper for smaller packets, large lutsJosh Blum2012-02-0213-20/+48
| * b100: sc8 mode not implemented errorJosh Blum2012-02-011-0/+4
| * b100: bump compat numbers for slave fifo modeJosh Blum2012-02-011-1/+1
| * B100: Modified TX send size to achieve 10.7Msps.Nick Foster2012-02-011-1/+1
| * B100 host code changes to remove TX padding, remove RX padding, increase max ...Nick Foster2012-02-011-1/+1
| * dsp rework: account for no sid used in tx vita pktJosh Blum2012-02-013-1/+4
| * dsp rework: tx trailer, scaling work (peak)Josh Blum2012-01-315-13/+32
| * gen2: added user setting regs api and user coreJosh Blum2012-01-3113-2/+122
| * dsp rework: work on scaling and args parsing on RX and TX dspJosh Blum2012-01-317-38/+60
| * dsp rework: implemented new scalefactor in rx dsp coreJosh Blum2012-01-318-19/+32
* | Fixing TX mixer disable, maxing out attenuation when not in use.Ben Hilburn2012-02-072-57/+39
* | Fixing ADF4351 dividers, even though they won't get used.Ben Hilburn2012-02-071-2/+2
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 22:56:54 +0000