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* ad9361: Added synchronization to IO and device classesAshish Chaudhari2014-08-133-20/+36
* ad9361: Cleaned up constants and macrosAshish Chaudhari2014-08-134-84/+67
* ad9361: Cleaned up errors and debug messagesAshish Chaudhari2014-08-121-45/+46
* ad9361: Converted stdint types to boost typesAshish Chaudhari2014-08-127-136/+133
* ad9361: Renamed ad9361_impl.c to ad9361_device.cppAshish Chaudhari2014-08-122-6/+1
* b200, ad9361: Cleanup up AD9361 driverAshish Chaudhari2014-08-1213-1553/+1122
* b200: Removed all AD9361 related firmwareAshish Chaudhari2014-08-123-85/+1
* Merge branch 'master' into ashish/cat_refactor_masterAshish Chaudhari2014-08-054-11/+35
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| * Merge branch 'maint'Martin Braun2014-07-314-11/+35
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| | * Merge branch 'maint' into uhd/bug492michael-west2014-07-307-49/+167
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| | | * tx fe corrections: fixing mixed tabs / spaces, other horrible whitespace cruftBen Hilburn2014-07-252-14/+11
| | | * Merge 'maint' into x300/bug513Ben Hilburn2014-07-252-3/+4
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| | | * | X300: Added UHD support for TX FEIan Buckley2014-07-182-1/+14
| | * | | Fix for BUG #492: UHD: set_time_unknown_pps() fails with GPSDO installedmichael-west2014-06-253-3/+17
* | | | | b200: Added variable rate SPI core for AD9361 and ADF4001Ashish Chaudhari2014-08-018-8/+159
* | | | | b200: Moved AD9361 driver to hostAshish Chaudhari2014-08-0118-131/+2872
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* | | / OctoClock firmware upgrade, added host driverNicholas Corgan2014-07-237-11/+17
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* | | Commented out warning if X300 reference clock fails to lock within 1 second d...michael-west2014-07-221-2/+3
* | | Fix for BUG #517: B200: Regression of power level on RXmichael-west2014-07-221-1/+1
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* | Updated copyright year.michael-west2014-07-171-1/+1
* | Fix for BUG #469michael-west2014-07-171-0/+2
* | - Changed variables from uint8_t to uint32_t so parsing of hex strings would ...michael-west2014-07-171-3/+3
* | Addressing comments from review.michael-west2014-07-172-15/+21
* | Fix for BUG #469: Bad/Empty GPS NMEA strings returned when the queries are m...michael-west2014-07-172-20/+108
* | Merge branch 'origin/b200/bug516' into maintBen Hilburn2014-07-171-4/+4
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| * | BUG #516: B210: Fails to Run with 30.72 MHz Clockmichael-west2014-07-101-1/+1
| * | Fix for BUG #516: B210: Fails to Run with 30.72 MHz Clockmichael-west2014-06-181-3/+3
| * | Fix for BUG #516: B210: Fails to Run with 30.72 MHz Clockmichael-west2014-06-181-3/+3
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* | Merge branch 'origin/ashish/rx_pcie_overflows' into maintBen Hilburn2014-07-172-3/+7
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| * | x300: Bugfix for overflows on PCIe at 200MS/sAshish Chaudhari2014-06-272-3/+7
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* | Merge branch 'origin/b200/bug512' into maintBen Hilburn2014-07-171-9/+15
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| * | Enhancement #512: B210: Need an Internal PPSmichael-west2014-06-131-9/+15
* | | Fix for BUG #527: N200: 50 Msps results in two tonesmichael-west2014-07-011-1/+2
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* | Merge branch 'origin/b200/bug500' into maint - Fixing B200 phase alignment issueBen Hilburn2014-06-163-3/+9
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| * - Changed XOR to OR for REG_DSP_RX_MUX flags.michael-west2014-06-121-3/+3
| * Fix for BUG #500: B210: RX channels are not phase alignedmichael-west2014-06-063-3/+9
* | Lots of bit-specific type work to fix compilation on older OSes.Ben Hilburn2014-05-214-15/+15
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* x300: adding include to fix builds on older systemsBen Hilburn2014-05-201-0/+1
* Fixing Bug #473 - Autoselection of VCO Frequency in DBSRX2Ben Hilburn2014-05-201-6/+8
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| * Fixed whitespace and added comment.michael-west2014-05-201-5/+6
| * Fix for BUG 473: UHD: DBSRX2 VCO Autoselect Failing / Wrong Frequency Rangemichael-west2014-05-131-3/+4
* | Fix for BUG 456: LED TX/RX colors backwards on X300michael-west2014-05-161-2/+2
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* Merge branch 'origin/martin/multi_usrp/bug_dc_offset' into maintBen Hilburn2014-05-081-5/+25
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| * multi_usrp: Throws warnings for some tree propsMartin Braun2014-05-051-5/+25
* | BUG #460: X300: GPGGA sensor most often empty, while RMC is usually OKmichael-west2014-05-061-1/+8
* | usrp2: fixed usrp2_card_burner.py and usrp_n2xx_simple_net_burner paths in in...Nicholas Corgan2014-05-062-4/+17
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* x300: Bumped FPGA compat number to 6.Ashish Chaudhari2014-04-281-1/+1
* x300: Changed bus_clk frequency to 166.67MHz.Ashish Chaudhari2014-04-281-1/+1
* x300: Bumped FPGA compat number to 5.Ashish Chaudhari2014-04-251-1/+1
* x300: Addressed review feedbackAshish Chaudhari2014-04-251-11/+13
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