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* B100: Firmware reset tweaks.Nick Foster2012-02-091-1/+1
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* dsp rework: implement 64 bit ticks, no secondsJosh Blum2012-02-0613-61/+63
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* B100: use FPGA external reset on initNick Foster2012-02-062-0/+7
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* b100/e100: unify rx/tx fifo clears into oneJosh Blum2012-02-044-14/+8
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* b100: delete some unused registers from mapJosh Blum2012-02-042-7/+0
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* dsp rework: move setting address of format registerJosh Blum2012-02-022-6/+4
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* dsp rework: work on usb wrapper for smaller packets, large lutsJosh Blum2012-02-0213-20/+48
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* b100: sc8 mode not implemented errorJosh Blum2012-02-011-0/+4
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* b100: bump compat numbers for slave fifo modeJosh Blum2012-02-011-1/+1
| | | | | | Conflicts: host/lib/usrp/b100/b100_impl.hpp
* B100: Modified TX send size to achieve 10.7Msps.Nick Foster2012-02-011-1/+1
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* B100 host code changes to remove TX padding, remove RX padding, increase max ↵Nick Foster2012-02-011-1/+1
| | | | allowed rate.
* dsp rework: account for no sid used in tx vita pktJosh Blum2012-02-013-1/+4
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* dsp rework: tx trailer, scaling work (peak)Josh Blum2012-01-315-13/+32
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* gen2: added user setting regs api and user coreJosh Blum2012-01-3113-2/+122
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* dsp rework: work on scaling and args parsing on RX and TX dspJosh Blum2012-01-317-38/+60
| | | | | This simplified some copy pasta in the io_impl.cpp files, and adds a place for sc8 tx mode in the tx dsp core code.
* dsp rework: implemented new scalefactor in rx dsp coreJosh Blum2012-01-318-19/+32
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* usrp1/b100: reenumeration loop with timeout only when foundJosh Blum2012-01-272-2/+6
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* Swap I/Q on transmitJason Abele2012-01-271-1/+1
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* usrp1/b100: handle longer reenumerations with loop and timeoutJosh Blum2012-01-262-34/+50
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* uhd: add samples per pkt option to rx streamerJosh Blum2012-01-263-3/+6
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* uhd: flush transport for new rx streamersJosh Blum2012-01-235-7/+5
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* usrp1: use fixed bit width integer for hashJosh Blum2012-01-171-14/+17
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* usrp: db manager tweak for contructor throwingJosh Blum2012-01-111-2/+2
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* usrp: compensate for other sc8 conversion gainJosh Blum2012-01-091-1/+3
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* sbx: fix dboard tuning to cache resultJosh Blum2012-01-054-23/+5
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* usrp1: initialize tick_rate prop (fixes readback)Josh Blum2012-01-051-1/+2
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* N210 R4 should be using LVDS TX clock, not CMOS.Nick Foster2012-01-041-4/+17
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* usrp2: fw fix for hal_uart_getc_noblock return codeJosh Blum2012-01-041-1/+1
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* e100: better error message for eeprom model errorJosh Blum2011-12-311-5/+11
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* Merge branch 'network_foo'Josh Blum2011-12-212-5/+5
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| * usrp2: use the socket to determine the device addrJosh Blum2011-12-202-5/+5
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* | usrp: added underflow_policy to tx streamer argsJosh Blum2011-12-205-1/+16
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* basic: minor fix for copy paste typoJosh Blum2011-12-201-1/+1
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* Make WBX v3+ TX set max attenuation when idleJason Abele2011-12-162-12/+21
| | | | | | | Because WBX v3+ uses digital step attenuator for TX gain control we can set max attenuation via ATR when WBX is in RX_ONLY or IDLE This will reduce the LO leakage during non-transmit times
* usrp1: fix div ratio for interp registerJosh Blum2011-12-151-1/+1
| | | | | The interp register was getting set 2x, now fixed! This bug was introduced w/ the streamer work.
* usrp1: fixed swapped sign on rx cordicJosh Blum2011-12-151-1/+1
| | | | | | | | | | | We used to swap I and Q to share converter functions with the newer products. Because of this, the sign on the cordic also had to be swapped. Now that USRP1 has its own converter routines and I and Q are correct, so should be the sign on the cordic. This was a bug introduced in master. TX should not be an issue, because there is no cordic and is adjusted digitally by the codec, after any potential swapping.
* tvrx: adjust returned lo freq to compensate for negative cordic shiftJosh Blum2011-12-151-0/+7
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* tvrx: fixes for tvrx since the property tree workJosh Blum2011-12-151-6/+6
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* uhd: typo fix for the error printJosh Blum2011-12-151-1/+1
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* usrp: better error message when dboard fails in initJosh Blum2011-12-151-1/+8
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* usrp: added mboard param to set time next ppsJosh Blum2011-12-121-3/+7
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* UHD will now print 'L' whenever a late packet is transmitted.Ben Hilburn2011-12-123-0/+9
| | | | | This is similiar to printing 'U' and 'S'. This functionality is not yet supported on the USRP1.
* usrp: rx dsp move init code into clear (like tx)Josh Blum2011-12-051-6/+7
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* Make TX disable mixer when idle to avoid LO leakageJason Abele2011-12-051-2/+2
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* uhd: work with stream clearingJosh Blum2011-12-055-13/+24
| | | | | | | | dont clear when using the compat device API tx clear also resets expected seqnum tx clear on usrp2 resets flow control monitor
* usrp1: set scale factor after setting converterJosh Blum2011-11-301-4/+4
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* b100: tweaks for fpga resets on initJosh Blum2011-11-221-11/+8
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* dbsrx: set initial freq and bw filter after clocks enabledJosh Blum2011-11-211-4/+8
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* usrp: clear dsp when making new streamerJosh Blum2011-11-217-0/+16
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* basic: fix basic db center freq to always zeroJosh Blum2011-11-201-2/+5
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