| Commit message (Collapse) | Author | Age | Files | Lines |
... | |
| | |
|
| | |
|
| |
| |
| |
| | |
enabled (prevent function from disabling frontends)
|
| |
| |
| |
| | |
get_tx_hints()
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
This adds a feature that is already present in e3xx and n230
products allowing to read back the fpga git hash the current
image has been built from.
The value is available via property tree at:
/mboards/0/fpga_version_hash
Note: A compatibility number bump is required, as otherwise the
register will always read back 0
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
|
| | |
|
| | |
|
| |
| |
| |
| |
| | |
- UHD and ZPU is now aware of Aurora SFP+ transceivers in the FPGA image
- Added script to exercise Aurora BIST features
|
|\| |
|
| |
| |
| |
| | |
There's an off-by-one error in base64_decode_value that results in undefined behaviour when it's passed `'\x7b'`
|
| |
| |
| |
| |
| |
| | |
This proved helpful on devices where the EEPROM is wrong about hardware
revision, and the EEPROM writing doesn't work, because the ADC self-test
fails due to being run for the wrong board revision.
|
|\| |
|
| |
| |
| |
| |
| |
| |
| | |
- The spectral distortion was begin caused by the DAC FIFO
underflowing. The fix was to run through the DAC sync
procedure which uses the falling edge clock to sample
the RefClk and sync it with the data clk
|
| |
| |
| |
| |
| |
| | |
- If there were duplicate IPs in the mboard eeprom, the last one would be selected instead of the first
- The default IP addresses (used for the case where the mboard eeprom can't be read) would overwrite the previous settings
- Added a warning for duplicate IP entries in the mboard eeprom
|
| |
| |
| |
| |
| | |
- This change ensures that the smallest frame size is chosen with dual ethernet
- It helps avoid any issues with using frame sizes larger than what the smaller link supports
|
| |
| |
| |
| |
| | |
- A dboard_base class can have multiple frontends (subdevs) and
the set_fe_connection needs to be able to distinguish between them
|
| |
| |
| |
| |
| | |
- Fixed an issue where 10GE on the HGS image presented a false warning for the link capacity
- Removed some unnecessary variables after cleanup
|
| | |
|
| | |
|
| | |
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
- rx_dsp_core: set_mux takes in a fe_connection obj
to determine IQ mapping and sampling mode parameters
- rx_dsp_core: Support a non-zero IF for downconversion
The current strategy applies a software DSP freq offset
which eats into the range of the CORDIC which is OK
because heterodyne assumes real-mode sampling
|
|\| |
|
| | |
|
|\|
| |
| |
| |
| |
| | |
Conflicts:
host/lib/usrp/cores/gpio_core_200.cpp
host/lib/usrp/dboard/db_ubx.cpp
|
| |
| |
| |
| |
| |
| |
| | |
- Disabled MAX2871 VCO auto selection for phase sync
- Added checks for new phase sync constraints recently published by Maxim
- Added dboard_clock_rate option for X300
- Adjusted timing of SYNC signal relative to dboard referenc clock
|
| | |
|
| |
| |
| |
| | |
- DB connection mapping is implemented in DDC chain. FE corrections module does not swap
|
| |
| |
| |
| |
| |
| |
| | |
- Made dboard_iface an interface! Removed PIMPL
- Added unit "BOTH" to dboard API and expanded GPIO API width to 32
- Removed gpio_debug_mux. No product ever used that
- Refactored gpio_atr cores to work with new dboard_iface
|
| |
| |
| |
| |
| |
| | |
- Moved dboard iface initialization to dboard_manager
- Added a restricted register function. Restricted dboards
don't expose their control iface in the property tree
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
- Added desired and coerced values and accessors to property
- Added support to register desired subscribers
- set APIs don't reallocate storage for a property value
- Renamed callback method registration APIs
- Registering 2 coercers or publishers for a property will throw
- Registering a coercer and a publisher for the same property will throw
|
| | |
|
| |
| |
| |
| |
| |
| |
| | |
- b200: compat 14
- b200mini: compat 5
- e3xx: compat 15
- x3xx: compat 20
|
|\|
| |
| |
| |
| |
| |
| | |
Conflicts:
host/lib/usrp/b200/b200_impl.hpp
host/lib/usrp/e300/e300_fpga_defs.hpp
host/lib/usrp/x300/x300_fw_common.h
|
| |
| |
| |
| |
| |
| |
| | |
- b200: compat 13
- b200mini: compat 4
- e3xx: compat 14
- x3xx: compat 19
|
| | |
|
| | |
|
| |
| |
| |
| |
| |
| |
| | |
- b200: compat 11
- b200mini: compat 2
- e300: compat 11
- x300: compat 15
|
| |
| |
| |
| |
| |
| | |
Compensate for headroom required to rotate a signal in
the CORDIC. Fixes some CORDIC-related clipping issues,
that reduced ENOB to 15 or 14.5 bits.
|
| |
| |
| |
| |
| | |
- e300: compat 13
- x300: compat 18
|
| | |
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
All device-specific CMake components are now registered in one place,
before the host/lib/ subdirs are sourced. This way, there are no
cyclic dependencies.
This solves the issue where ENABLE_X300=Off could disable USB, but
preserves the fix where ENABLE_X300=Off would still build some X300
codes.
|
| |
| |
| |
| |
| |
| |
| | |
- b200: compat 12
- b200mini: compat 3
- e300: compat 12
- x300: compat 17
|
|\ \
| | |
| | |
| | |
| | |
| | | |
Conflicts:
host/lib/usrp/cores/CMakeLists.txt
host/lib/usrp/x300/x300_impl.hpp
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
- Refactored GPIO ATR definitions
- Added new 3000 core with a more efficient API
- Added a separate db_gpio_atr core to control the ATR bus
- Ported b2xx, e3xx and x3xx to the new core
- Minor cleanup
|
| | | |
|
| | |
| | |
| | |
| | | |
- New and improved DRAM DMA FIFO
|
| | | |
|
|/ /
| |
| |
| |
| | |
- Added HG vs HGS detection logic
- Added DMA FIFO configuration code
|
| |
| |
| |
| |
| |
| |
| | |
- b200: compat 11
- b200mini: compat 2
- e300: compat 11
- x300: compat 15
|
|/
|
|
|
|
| |
Compensate for headroom required to rotate a signal in
the CORDIC. Fixes some CORDIC-related clipping issues,
that reduced ENOB to 15 or 14.5 bits.
|