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| * | | x300: support new 120 MHz bandwidth versions of the NI-branded X310sBrooks2014-12-222-84/+102
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| * | | Merge branch 'maint'Martin Braun2014-12-162-2/+2
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| * | | | x300: Fixed minor issues in X300 clk codeAshish Chaudhari2014-12-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | - Bugfix for #638 - get_ref_locked will check lock status one last time before giving up
| * | | | x300: Made use of new CHDR packing routinesMartin Braun2014-12-031-43/+9
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| * | | | Merge branch 'maint'Martin Braun2014-12-021-1/+10
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| * | | | | uhd: replaced the `images_error` with a generic utility errorBen Hilburn2014-11-211-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Deleted images.*, moved functionality to paths.* - Applies for all devices that check FPGA or FW compat numbers - Adds generic utility search tool
* | | | | | x300: Timing changes for the new DAC data interfaceAshish Chaudhari2015-03-122-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Switched DAC to DCI delay bypass mode because we shift the DCI in the FPGA now - Changed LMK control to add 900ps delay to DAC clocks to be consistent with the radio_clk delay. The timing analyzer is expecting the two clocks to have a 0 deg phase diff.
* | | | | | x300: Multiple firmware fixes for VivadoAshish Chaudhari2015-02-171-2/+2
| |_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Refactored SFP+ hotplug handler - GigE link state comes from SFP+ status and PHY status - Multiple tracing enhancements - Bumped firmware compat number to 4 - Bumpled FPGA compat number to 10
* | | | | Merging new UHD_IMAGES_DIR utilities and bug fixes.Ben Hilburn2015-01-271-7/+7
| |_|_|/ |/| | | | | | | | | | | Also includes NI-USRP Windows Registry Key fixes.
* | | | x300: Fix for BUG #655: X300: Device Time Not Getting Set from GPSDOmichael-west2015-01-121-8/+6
| |_|/ |/| | | | | | | | - Moved setting of tick rate before setting of PPS time
* | | e300,x300: Bumped FPGA compat numberAshish Chaudhari2014-12-161-1/+1
| | | | | | | | | | | | | | | - X300: FPGA compat 9 - E300: FPGA compat 5
* | | e300,x300: Moved LED register space as not to overlap w/ GPIOsAshish Chaudhari2014-12-161-1/+1
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* | x300: Fixed FC window issue (was off by one)Martin Braun2014-12-021-1/+10
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* x300: Clarified FPGA compat error messageMartin Braun2014-11-211-5/+10
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* x300: Cleaned up DAC ctrl and clock init logicAshish Chaudhari2014-11-066-201/+318
| | | | | | | | | | | - DAC: Squashed configuration into 2 main operations: reset and reset_and_resync - DAC: Put in sleep mode during configuration - DAC: Synchronize only if streaming to more than one DAC - DAC: Use falling edge sync mode - DAC: Fixed power up/down settings - DAC: Frontend sync failure is fatal - Clocks: Refactored clock source change logic - Clocks: Cleaned up init and lock-check sequence
* x300: Fixed typo in io_implMartin Braun2014-11-041-1/+1
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* x300,nirio: Added support for NI-RIO 14.0Ashish Chaudhari2014-10-103-20/+17
| | | | | | | | | - Split niriok_proxy interfaces to support NI-RIO <=13.0 and >=14.0 kernel interfaces - Fixed multi-session race conditions by synchronizing niriok_proxy access - Fixed bug switching from NI LV-FPGA access to UHD access by changing how devices are hashed into a reservation table - Fixed calculation of FRAC values for CBX and SBX LO tuning by rounding instead of truncating - Fixed bug that was not setting two MSBs for band select configuration of CBX LO - Submitting on behalf of Patrick Sisterhen, Matthew Crymble
* x300: Reduced the TX buffer from 576K to 520KAshish Chaudhari2014-10-092-2/+2
| | | | | - Trading performance for stability. This helps meet timing at the cost of a shorter processing time window between sends. - Bumped FPGA compat number to 8
* Merge branch 'maint'Martin Braun2014-09-257-55/+162
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| * x300: Reverted back to no analog delay for DAC ref clocksmichael-west2014-09-251-5/+0
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| * x300: added reset and resync of ADCs and DACs when changing reference clockmichael-west2014-09-256-54/+166
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* | Merge branch 'maint'Martin Braun2014-09-241-0/+1
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| * x300: Added output sync for DAC reference clocksMartin Braun2014-09-241-0/+1
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* | Give user the option to ignore daughterboard's calibration file at runtimeNicholas Corgan2014-09-022-2/+8
| | | | | | | | | | * Add "ignore-cal-file" to the uhd::device_addr_t arguments * Added documentation for new feature
* | Added missing pure virtual destructors to base classesNicholas Corgan2014-09-016-4/+22
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* | Merge branch 'maint'Martin Braun2014-09-011-1/+1
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| * x300_dboard_iface: added UHD_UNUSED() macro to unused parameters in ↵Nicholas Corgan2014-08-291-1/+1
| | | | | | | | | | | | set_clock_enabled() * Removes GCC warning about unused parameters
* | Merge branch 'maint'Martin Braun2014-08-183-43/+37
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| * Bumping FPGA compat to 7.michael-west2014-08-181-1/+1
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| * Changed analog delay on DAC reference and radio clocks from 1075ps to 900psmichael-west2014-08-181-4/+4
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| * - Fixes for channel alignmentmichael-west2014-08-182-42/+36
| | | | | | | | | | | | | | | | | | | | - Added analog delay for radio clock - Added analog delay for DAC reference clocks - Removed resetting of clock control - Removed setting of reference clock and PPS to external sources during initialization - Fixes for set_time_unknown_pps - Removed wait for PPS edge after setting time from GPSDO - Changed set_time_unknonw_pps to time out based on system time rather than device VITA time
* | Merge branch 'maint'Martin Braun2014-07-312-10/+22
|\| | | | | | | | | Conflicts: host/utils/usrp_burn_mb_eeprom.cpp
| * Merge branch 'maint' into uhd/bug492michael-west2014-07-303-28/+106
| |\ | | | | | | | | | | | | Conflicts: host/lib/usrp/b200/b200_impl.cpp
| | * tx fe corrections: fixing mixed tabs / spaces, other horrible whitespace cruftBen Hilburn2014-07-252-14/+11
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| | * Merge 'maint' into x300/bug513Ben Hilburn2014-07-251-2/+3
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| | * | X300: Added UHD support for TX FEIan Buckley2014-07-182-1/+14
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| * | | Fix for BUG #492: UHD: set_time_unknown_pps() fails with GPSDO installedmichael-west2014-06-251-2/+4
| | | | | | | | | | | | | | | | - Added polling for PPS time change after setting time from GPSDO.
* | | | OctoClock firmware upgrade, added host driverNicholas Corgan2014-07-231-1/+2
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | * OctoClock can communicate with UHD over Ethernet * Can read NMEA strings from GPSDO and send to host * Added multi_usrp_clock class for clock devices * uhd::device can now filter to return only USRP devices or clock devices * New OctoClock bootloader can accept firmware download over Ethernet * Added octoclock_burn_eeprom,octoclock_firmware_burner utilities * Added test_clock_synch example to show clock API
* | | Commented out warning if X300 reference clock fails to lock within 1 second ↵michael-west2014-07-221-2/+3
| |/ |/| | | | | during initialization. Sometimes it takes longer and that is OK.
* | Fix for BUG #469michael-west2014-07-171-0/+2
| | | | | | | | - Added mutex for write_uart()
* | Addressing comments from review.michael-west2014-07-171-7/+9
| | | | | | | | | | | | - Corrected types of some variables to be boost types. - Removed debugging code accidentally left in. - Changed some compiled out error messages to log messages.
* | Fix for BUG #469: Bad/Empty GPS NMEA strings returned when the queries are ↵michael-west2014-07-171-15/+74
| | | | | | | | | | | | | | | | | | made in a random wait iterative fashion Fix for BUG #460: X300: GPGGA sensor most often empty, while RMC is usually OK - Added checksum verification of NMEA strings - Improved handling of short or malformed strings - Fixed GPSDO data synchronization between X300 firmware and host
* | x300: Bugfix for overflows on PCIe at 200MS/sAshish Chaudhari2014-06-272-3/+7
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* Lots of bit-specific type work to fix compilation on older OSes.Ben Hilburn2014-05-214-15/+15
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* x300: adding include to fix builds on older systemsBen Hilburn2014-05-201-0/+1
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* Fix for BUG 456: LED TX/RX colors backwards on X300michael-west2014-05-161-2/+2
| | | | - Corrected bit masks so TX will light the red LED and RX will light the green LED
* x300: Bumped FPGA compat number to 6.Ashish Chaudhari2014-04-281-1/+1
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* x300: Changed bus_clk frequency to 166.67MHz.Ashish Chaudhari2014-04-281-1/+1
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* x300: Bumped FPGA compat number to 5.Ashish Chaudhari2014-04-251-1/+1
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* x300: Addressed review feedbackAshish Chaudhari2014-04-251-11/+13
| | | | | - Fixed synchronization for unclaim - Removed stray RIO addr space set
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