| Commit message (Collapse) | Author | Age | Files | Lines |
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Reviewed-By: Michael West <michael.west@ettus.com>
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types)
- Also removes all references to boost/cstdint.hpp and replaces it with
stdint.h (The 'correct' replacement would be <cstdint>, but not all of our
compilers support that).
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If a daughterboard does not have a time/cmd property then no subscriber
should be added to the motherboard time/cmd property.
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This is a temporary workaround to make PCIe available on lower rates.
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Reviewed-By: Derek Kozel <derek.kozel@ettus.com>
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- Added LED controller objects for each block port in radio
- Added desired subscribers for each frontend's antenna property that
updates LED ATR values
Reviewed-By: Martin Braun <martin.braun@ettus.com>
Reviewed-By: Marcus Müller <marcus.mueller@ettus.com>
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- The value of db_eeprom_t being written was stale due to a caching bug
- Updated subscriber for db_eeprom_t to write the EEPROM state *and*
cache it locally
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Reviewed-By: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Martin Braun <martin.braun@ettus.com>
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These are USRP RIO (X310) devices with TwinRX daughter-boards.
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This provides the GPS fixes.
Conflicts:
host/CMakeLists.txt
tools/debs/upload_debs.sh
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- Optimize writes so full 32-bit words are written at a time
- Simplify UART so it does not strip or add characters
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This proved helpful on devices where the EEPROM is wrong about hardware
revision, and the EEPROM writing doesn't work, because the ADC self-test
fails due to being run for the wrong board revision.
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- Also updated images package.
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enabled (prevent function from disabling frontends)
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get_tx_hints()
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This adds a feature that is already present in e3xx and n230
products allowing to read back the fpga git hash the current
image has been built from.
The value is available via property tree at:
/mboards/0/fpga_version_hash
Note: A compatibility number bump is required, as otherwise the
register will always read back 0
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- UHD and ZPU is now aware of Aurora SFP+ transceivers in the FPGA image
- Added script to exercise Aurora BIST features
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There's an off-by-one error in base64_decode_value that results in undefined behaviour when it's passed `'\x7b'`
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This proved helpful on devices where the EEPROM is wrong about hardware
revision, and the EEPROM writing doesn't work, because the ADC self-test
fails due to being run for the wrong board revision.
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- The spectral distortion was begin caused by the DAC FIFO
underflowing. The fix was to run through the DAC sync
procedure which uses the falling edge clock to sample
the RefClk and sync it with the data clk
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- If there were duplicate IPs in the mboard eeprom, the last one would be selected instead of the first
- The default IP addresses (used for the case where the mboard eeprom can't be read) would overwrite the previous settings
- Added a warning for duplicate IP entries in the mboard eeprom
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- This change ensures that the smallest frame size is chosen with dual ethernet
- It helps avoid any issues with using frame sizes larger than what the smaller link supports
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- A dboard_base class can have multiple frontends (subdevs) and
the set_fe_connection needs to be able to distinguish between them
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- Fixed an issue where 10GE on the HGS image presented a false warning for the link capacity
- Removed some unnecessary variables after cleanup
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- rx_dsp_core: set_mux takes in a fe_connection obj
to determine IQ mapping and sampling mode parameters
- rx_dsp_core: Support a non-zero IF for downconversion
The current strategy applies a software DSP freq offset
which eats into the range of the CORDIC which is OK
because heterodyne assumes real-mode sampling
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Conflicts:
host/lib/usrp/cores/gpio_core_200.cpp
host/lib/usrp/dboard/db_ubx.cpp
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- Disabled MAX2871 VCO auto selection for phase sync
- Added checks for new phase sync constraints recently published by Maxim
- Added dboard_clock_rate option for X300
- Adjusted timing of SYNC signal relative to dboard referenc clock
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- DB connection mapping is implemented in DDC chain. FE corrections module does not swap
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- Made dboard_iface an interface! Removed PIMPL
- Added unit "BOTH" to dboard API and expanded GPIO API width to 32
- Removed gpio_debug_mux. No product ever used that
- Refactored gpio_atr cores to work with new dboard_iface
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