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- Load EEPROM data into firmware memory to access from there instead of driving the I2C bus directly
- Fixed firmware performance issues by removing the popcntll() function and reducing frequency of background tasks to once every 10ms
- Added x300_mb_eeprom_iface to handle cases of devices with older and newer firmware
- Added checks for claim to device before driving the I2C bus
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types)
- Also removes all references to boost/cstdint.hpp and replaces it with
stdint.h (The 'correct' replacement would be <cstdint>, but not all of our
compilers support that).
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These are USRP RIO (X310) devices with TwinRX daughter-boards.
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This adds a feature that is already present in e3xx and n230
products allowing to read back the fpga git hash the current
image has been built from.
The value is available via property tree at:
/mboards/0/fpga_version_hash
Note: A compatibility number bump is required, as otherwise the
register will always read back 0
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- UHD and ZPU is now aware of Aurora SFP+ transceivers in the FPGA image
- Added script to exercise Aurora BIST features
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Conflicts:
host/lib/usrp/b200/b200_impl.hpp
host/lib/usrp/e300/e300_fpga_defs.hpp
host/lib/usrp/x300/x300_fw_common.h
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- Added HG vs HGS detection logic
- Added DMA FIFO configuration code
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This preps the code for merging common registers altogether.
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- radio_rst was being asserted to reset the capture iface IDELAYs but
that was excessive and had adverse effects on the rest of the radio
- Replaced radio_rst with a localized IDELAYCTRL reset
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- Everytime the LMK is configured, we do the following:
- Reset all LMK regs
- Wait for LMK lock
- Reset radio_clk PLL in FPGA
- Wait for FPGA PLL to lock
- Assert radio_rst which resets downstream radio logic
- This address the intermittent self-cal failures due to uncalibrated IDELAY taps
- Bumped FPGA compat to 12
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- Added new PCIe and MB PIDs for new boards
- Added an error if MB PID is invalid
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- Self-calibration routine steps through various values of LMK
delay to detect metastability in the SSCLK -> radio_clk crossing
and computes an ideal delay for the ADC clock.
- Self calibration is triggered at startup if the self_cal_adc_delay
device arg is specified
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- Added DMA enabled states to DMA logic to allow for hardware data flushing during init.
- niusrprio_session will now check for FPGA busy before downloading
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PPS on external input on X3xx
- Fixed behavior of PPS and clock references to be consistent and intuitive.
-- Added detection of clock reference and PPS.
-- Changed order of precedence to external, gpsdo, internal for default of clock and PPS.
-- Throws runtime error if the user requests a reference clock or PPS that is not present.
- Bumped FPGA compatibility to 4.
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