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path: root/host/lib/usrp/x300/x300_impl.hpp
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* x300: Throttle MTU to 3000 for PCIe to avoid underrunsMartin Braun2016-10-251-1/+4
| | | | This is a temporary workaround to make PCIe available on lower rates.
* bugfix: db eeprom id not being written for X3x0Ashish Chaudhari2016-09-271-1/+0
| | | | | | | | - The value of db_eeprom_t being written was stale due to a caching bug - Updated subscriber for db_eeprom_t to write the EEPROM state *and* cache it locally Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
* Correct maximum link rates for 1GE and 10GEMarcus Müller2016-09-271-5/+11
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* Merging RFNoC support for X310Martin Braun2016-08-091-201/+60
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* x300: Fixed false link capacity warning and cleaned up some codePaul David2016-05-131-2/+0
| | | | | - Fixed an issue where 10GE on the HGS image presented a false warning for the link capacity - Removed some unnecessary variables after cleanup
* transport optimize: Integrated the transport offloading into the X3XX codebasePaul David2016-04-181-7/+37
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* dboard_iface: Added method to configure front connection and settingsAshish Chaudhari2016-03-211-0/+1
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* Merge branch 'maint'Ashish Chaudhari2016-02-181-0/+1
|\ | | | | | | | | | | Conflicts: host/lib/usrp/cores/gpio_core_200.cpp host/lib/usrp/dboard/db_ubx.cpp
| * UBX: Phase synchronizationmichael-west2016-02-181-0/+1
| | | | | | | | | | | | | | - Disabled MAX2871 VCO auto selection for phase sync - Added checks for new phase sync constraints recently published by Maxim - Added dboard_clock_rate option for X300 - Adjusted timing of SYNC signal relative to dboard referenc clock
* | dboard: Added restricted dboard registration capabilityAshish Chaudhari2016-02-161-1/+0
| | | | | | | | | | | | - Moved dboard iface initialization to dboard_manager - Added a restricted register function. Restricted dboards don't expose their control iface in the property tree
* | Merge branch 'maint'Ashish Chaudhari2015-12-151-0/+1
|\| | | | | | | | | | | | | Conflicts: host/lib/usrp/b200/b200_impl.hpp host/lib/usrp/e300/e300_fpga_defs.hpp host/lib/usrp/x300/x300_fw_common.h
| * E300/X300: Add VITA time synchronization on internal signalmichael-west2015-12-101-0/+1
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| * cores: Corrected scaling_adjustment calculationIan Buckley2015-09-031-0/+2
| | | | | | | | | | | | Compensate for headroom required to rotate a signal in the CORDIC. Fixes some CORDIC-related clipping issues, that reduced ENOB to 15 or 14.5 bits.
* | Merge branch 'ashish/gpio_atr_redux' into master-stagingAshish Chaudhari2015-10-151-7/+5
|\ \ | | | | | | | | | | | | | | | Conflicts: host/lib/usrp/cores/CMakeLists.txt host/lib/usrp/x300/x300_impl.hpp
| * | usrp3: Added new GPIO ATR 3000 coreAshish Chaudhari2015-09-291-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | - Refactored GPIO ATR definitions - Added new 3000 core with a more efficient API - Added a separate db_gpio_atr core to control the ATR bus - Ported b2xx, e3xx and x3xx to the new core - Minor cleanup
* | | x300: Made DRAM FIFO size software configurableAshish Chaudhari2015-09-161-0/+1
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* | | x300: Added DMA FIFO support to X300Ashish Chaudhari2015-09-161-2/+9
|/ / | | | | | | | | - Added HG vs HGS detection logic - Added DMA FIFO configuration code
* / cores: Corrected scaling_adjustment calculationIan Buckley2015-09-081-0/+2
|/ | | | | | Compensate for headroom required to rotate a signal in the CORDIC. Fixes some CORDIC-related clipping issues, that reduced ENOB to 15 or 14.5 bits.
* x300: Used new soft register API for X300 registersAshish Chaudhari2015-08-041-45/+7
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* x300: Added a comprehensive radio reset sequenceAshish Chaudhari2015-07-221-2/+1
| | | | | | | | | | | - Everytime the LMK is configured, we do the following: - Reset all LMK regs - Wait for LMK lock - Reset radio_clk PLL in FPGA - Wait for FPGA PLL to lock - Assert radio_rst which resets downstream radio logic - This address the intermittent self-cal failures due to uncalibrated IDELAY taps - Bumped FPGA compat to 12
* x300: Added extended ADC self-testAshish Chaudhari2015-07-191-0/+2
| | | | | - New device arg "ext_adc_self_test" triggers the test - ext_adc_self_test=<time> runs the test for "time" seconds
* Added uhd::image_loader class and uhd_image_loader utilityNicholas Corgan2015-07-151-1/+3
| | | | | | * Single class for loading firmware/FPGA images onto devices instead of multiple utilities * Loading functions are registered for each device, corresponding to their --args="type=foo" name * Deprecation warnings added to all product-specific image loading utilities
* x300: Added self-cal to tune ADC source-sync data delaysAshish Chaudhari2015-07-071-8/+17
| | | | | | | - Self-calibration routine steps through various values of IDELAY taps on the SS data bits to detect metastability in the capture interface and computes an ideal delay tap value - Self calibration is triggered at device creation
* x300: Added self-cal to tune ADC clk delay at startupAshish Chaudhari2015-07-011-1/+36
| | | | | | | | - Self-calibration routine steps through various values of LMK delay to detect metastability in the SSCLK -> radio_clk crossing and computes an ideal delay for the ADC clock. - Self calibration is triggered at startup if the self_cal_adc_delay device arg is specified
* Merge branch 'maint'Martin Braun2015-04-101-2/+2
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| * Increase command FIFO depth of N2x0 and X3x0 to 64.michael-west2015-04-101-2/+2
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* | Merge branch 'maint'Martin Braun2015-04-061-0/+1
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| * uhd: Add ability to get and set command time through dboard_iface.michael-west2015-04-031-0/+1
| | | | | | | | | | This creates a wb_iface child class called timed_wb_iface, which adds support for timed commands.
| * x300: Cleaned up DAC ctrl and clock init logicAshish Chaudhari2014-11-061-2/+10
| | | | | | | | | | | | | | | | | | | | | | - DAC: Squashed configuration into 2 main operations: reset and reset_and_resync - DAC: Put in sleep mode during configuration - DAC: Synchronize only if streaming to more than one DAC - DAC: Use falling edge sync mode - DAC: Fixed power up/down settings - DAC: Frontend sync failure is fatal - Clocks: Refactored clock source change logic - Clocks: Cleaned up init and lock-check sequence
* | B200: UHD support for FPGPIO connector on REV6+ boards.Ian Buckley2015-03-091-3/+3
| | | | | | | | | | | | - GPIO on UART connector all board Revs - Consolidated fpgpio_bitbang into fpgpio example and renamed it gpio - Changed FP_GPIO readback address to match X300
* | x300: Cleaned up DAC ctrl and clock init logicAshish Chaudhari2014-11-131-2/+10
|/ | | | | | | | | | | - DAC: Squashed configuration into 2 main operations: reset and reset_and_resync - DAC: Put in sleep mode during configuration - DAC: Synchronize only if streaming to more than one DAC - DAC: Use falling edge sync mode - DAC: Fixed power up/down settings - DAC: Frontend sync failure is fatal - Clocks: Refactored clock source change logic - Clocks: Cleaned up init and lock-check sequence
* x300,nirio: Added support for NI-RIO 14.0Ashish Chaudhari2014-10-101-1/+1
| | | | | | | | | - Split niriok_proxy interfaces to support NI-RIO <=13.0 and >=14.0 kernel interfaces - Fixed multi-session race conditions by synchronizing niriok_proxy access - Fixed bug switching from NI LV-FPGA access to UHD access by changing how devices are hashed into a reservation table - Fixed calculation of FRAC values for CBX and SBX LO tuning by rounding instead of truncating - Fixed bug that was not setting two MSBs for band select configuration of CBX LO - Submitting on behalf of Patrick Sisterhen, Matthew Crymble
* x300: Reduced the TX buffer from 576K to 520KAshish Chaudhari2014-10-091-1/+1
| | | | | - Trading performance for stability. This helps meet timing at the cost of a shorter processing time window between sends. - Bumped FPGA compat number to 8
* Merge branch 'maint'Martin Braun2014-09-251-0/+2
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| * x300: added reset and resync of ADCs and DACs when changing reference clockmichael-west2014-09-251-0/+2
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* | Give user the option to ignore daughterboard's calibration file at runtimeNicholas Corgan2014-09-021-0/+1
|/ | | | | * Add "ignore-cal-file" to the uhd::device_addr_t arguments * Added documentation for new feature
* tx fe corrections: fixing mixed tabs / spaces, other horrible whitespace cruftBen Hilburn2014-07-251-1/+1
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* X300: Added UHD support for TX FEIan Buckley2014-07-181-0/+2
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* x300: Bugfix for overflows on PCIe at 200MS/sAshish Chaudhari2014-06-271-1/+5
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* Lots of bit-specific type work to fix compilation on older OSes.Ben Hilburn2014-05-211-2/+2
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* x300: Changed bus_clk frequency to 166.67MHz.Ashish Chaudhari2014-04-281-1/+1
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* x300: Added synchronization between device claiming and checking.Ashish Chaudhari2014-04-241-0/+1
| | | | | - We now maintain a registry of pcie ZPU transports - Added static mutex for claimer
* x300: Added max link rate infoMartin Braun2014-04-101-0/+4
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* x300: Fix the assumed max header sizeMartin Braun2014-03-281-0/+9
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* Modified reference clock lock check to only be performed on Rev E or later.michael-west2014-03-171-0/+2
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* Merge clock and PPS fixes.Ben Hilburn2014-03-151-5/+7
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| * Addressed comments from review.michael-west2014-03-151-5/+6
| | | | | | | | | | | | - Fixed typos. - Renamed reset() to reset_clocks(). - Created wait_for_ref_locked() function.
| * - Fix for BUG #264: ./test_pps_input --source external passes even with no 1 ↵Michael West2014-02-181-0/+1
| | | | | | | | | | | | | | | | | | | | PPS on external input on X3xx - Fixed behavior of PPS and clock references to be consistent and intuitive. -- Added detection of clock reference and PPS. -- Changed order of precedence to external, gpsdo, internal for default of clock and PPS. -- Throws runtime error if the user requests a reference clock or PPS that is not present. - Bumped FPGA compatibility to 4.
* | Merge Ethernet, MTU, and frame size fixes.Ben Hilburn2014-03-141-1/+1
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| * | x300 mtu: Removed magic number, minor manual updatesMartin Braun2014-02-181-1/+1
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