| Commit message (Collapse) | Author | Age | Files | Lines |
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- Refactored SFP+ hotplug handler
- GigE link state comes from SFP+ status and PHY status
- Multiple tracing enhancements
- Bumped firmware compat number to 4
- Bumpled FPGA compat number to 10
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- X300: FPGA compat 9
- E300: FPGA compat 5
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- Trading performance for stability. This helps meet timing at the cost of a shorter processing time window between sends.
- Bumped FPGA compat number to 8
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PPS on external input on X3xx
- Fixed behavior of PPS and clock references to be consistent and intuitive.
-- Added detection of clock reference and PPS.
-- Changed order of precedence to external, gpsdo, internal for default of clock and PPS.
-- Throws runtime error if the user requests a reference clock or PPS that is not present.
- Bumped FPGA compatibility to 4.
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