aboutsummaryrefslogtreecommitdiffstats
path: root/host/lib/usrp/x300/x300_fw_common.h
Commit message (Collapse)AuthorAgeFilesLines
* x300/mpmd: Port all RFNoC devices to the new RFNoC frameworkMartin Braun2019-11-261-1/+1
| | | | | | | Co-Authored-By: Alex Williams <alex.williams@ni.com> Co-Authored-By: Sugandha Gupta <sugandha.gupta@ettus.com> Co-Authored-By: Brent Stapleton <brent.stapleton@ettus.com> Co-Authored-By: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
* cores: Update rx_frontend_gen3.v controls for 1/4-rate mixerMartin Braun2018-09-251-1/+1
| | | | | | | This tracks the changes on rx_frontend_gen3.v, which was updated to use a quarter-rate downconverter instead of a generic CORDIC. The X3x0 FPGA compat number is incremented as the rx_frontend is part of the device architecture rather than an RFNoC block.
* x300: Fixed processor clock rate in ZPU firmwareAshish Chaudhari2018-02-231-2/+2
| | | | | - Fix for regression that was introduced after the bus_clk freq change - Firmware compat number bumped to 6.0 (was 5.2)
* rfnoc,x300: Multiple clocking changesAshish Chaudhari2018-02-211-1/+1
| | | | | | - Moved bus_clk <=> ce_clk crossing to axi_wrapper in FPGA which resulted in a noc_shell compat bump - Change x300 bus_clk frequency to 187.5 MHz
* uhd: Update license headersMartin Braun2018-02-191-1/+2
| | | | | | | All copyright is now attributed to "Ettus Research, a National Instruments company". SPDX headers were also updated to latest version 3.0.
* usrp3: Changes for Vivado 2017.4Ashish Chaudhari2018-01-241-1/+1
| | | | | | - Bumped compat number for e3xx, n230, x3xx, n3xx - Updated images package for e3xx, n230, x3xx, n3xx - Updated fpga-src submodule
* Move all license headers to SPDX format.Martin Braun2017-12-221-12/+1
|
* X3xx: Incremented firmware compat version minorPaul David2017-06-301-1/+1
|
* X3xx: Updated firmware to support reading FPGA image dataPaul David2017-06-301-0/+16
|
* X300: Prevent MB EEPROM Corruptionmichael-west2017-01-101-1/+28
| | | | | | | - Load EEPROM data into firmware memory to access from there instead of driving the I2C bus directly - Fixed firmware performance issues by removing the popcntll() function and reducing frequency of background tasks to once every 10ms - Added x300_mb_eeprom_iface to handle cases of devices with older and newer firmware - Added checks for claim to device before driving the I2C bus
* x300: Bumped FPGA compat num (is now: 0x21 == 33) and FW compat num (is now 5)Martin Braun2016-08-231-2/+2
| | | | - Also updated images package.
* Merging RFNoC support for X310Martin Braun2016-08-091-1/+1
|
* b2xx,e3xx,x300: Bumped FPGA compat numbers after incompatible maint mergeAshish Chaudhari2015-12-151-1/+1
| | | | | | | - b200: compat 14 - b200mini: compat 5 - e3xx: compat 15 - x3xx: compat 20
* b2xx,e3xx,x300: Bumped FPGA compat numbers after SW time-sync changesAshish Chaudhari2015-12-101-1/+1
| | | | | | | - b200: compat 13 - b200mini: compat 4 - e3xx: compat 14 - x3xx: compat 19
* Bumped FPGA compat numbers for B200, X300, and E300.michael-west2015-12-101-1/+1
|
* b2xx,e3xx,x300: Bumped compat numbers for 3.9.1 UHD releaseAshish Chaudhari2015-09-031-1/+1
| | | | | | | - b200: compat 11 - b200mini: compat 2 - e300: compat 11 - x300: compat 15
* b200,e300,x300: Updated compat number for release 3.9.0Ashish Chaudhari2015-08-141-1/+1
| | | | | | - b200: compat 10 - e300: compat 10 - x300: compat 14
* x300: Removed radio_rst assertion codeAshish Chaudhari2015-07-231-1/+1
| | | | | | - radio_rst was being asserted to reset the capture iface IDELAYs but that was excessive and had adverse effects on the rest of the radio - Replaced radio_rst with a localized IDELAYCTRL reset
* x300: Added a comprehensive radio reset sequenceAshish Chaudhari2015-07-221-1/+1
| | | | | | | | | | | - Everytime the LMK is configured, we do the following: - Reset all LMK regs - Wait for LMK lock - Reset radio_clk PLL in FPGA - Wait for FPGA PLL to lock - Assert radio_rst which resets downstream radio logic - This address the intermittent self-cal failures due to uncalibrated IDELAY taps - Bumped FPGA compat to 12
* x300: Addressed code review feedback for Rev7+ supportAshish Chaudhari2015-07-201-0/+1
|
* x300: Added HW rev compat number supportAshish Chaudhari2015-07-181-1/+1
| | | | | - Added new field "revision_compat" to mb_eeprom - Enforce a revision_compat of 7
* x300: Bumped max HW rev to 8Martin Braun2015-07-161-1/+1
|
* Updated compat numbers for B2x0 and X3x0Martin Braun2015-07-141-1/+1
| | | | | - B2x0: FW compat number (goes with previous firmware update) - X3x0: Max HW rev number
* Merge branch 'maint'Martin Braun2015-07-141-0/+1
|\ | | | | | | | | | | | | | | | | | | Conflicts: fpga-src host/CMakeLists.txt host/cmake/Modules/UHDVersion.cmake host/lib/usrp/b200/b200_impl.hpp host/lib/usrp/e300/e300_fpga_defs.hpp host/lib/usrp/x300/x300_fw_common.h
| * x300: Added max hw rev checkingMartin Braun2015-07-141-0/+1
| |
* | x300: Bumped FPGA compat number to 11Ashish Chaudhari2015-07-071-1/+1
| |
* | x300: Multiple firmware fixes for VivadoAshish Chaudhari2015-02-171-2/+2
|/ | | | | | | | - Refactored SFP+ hotplug handler - GigE link state comes from SFP+ status and PHY status - Multiple tracing enhancements - Bumped firmware compat number to 4 - Bumpled FPGA compat number to 10
* e300,x300: Bumped FPGA compat numberAshish Chaudhari2014-12-161-1/+1
| | | | | - X300: FPGA compat 9 - E300: FPGA compat 5
* x300: Reduced the TX buffer from 576K to 520KAshish Chaudhari2014-10-091-1/+1
| | | | | - Trading performance for stability. This helps meet timing at the cost of a shorter processing time window between sends. - Bumped FPGA compat number to 8
* Bumping FPGA compat to 7.michael-west2014-08-181-1/+1
|
* x300: Bumped FPGA compat number to 6.Ashish Chaudhari2014-04-281-1/+1
|
* x300: Bumped FPGA compat number to 5.Ashish Chaudhari2014-04-251-1/+1
|
* - Fix for BUG #264: ./test_pps_input --source external passes even with no 1 ↵Michael West2014-02-181-1/+1
| | | | | | | | | | PPS on external input on X3xx - Fixed behavior of PPS and clock references to be consistent and intuitive. -- Added detection of clock reference and PPS. -- Changed order of precedence to external, gpsdo, internal for default of clock and PPS. -- Throws runtime error if the user requests a reference clock or PPS that is not present. - Bumped FPGA compatibility to 4.
* Merging USRP X300 and X310 support!!Ben Hilburn2014-02-041-0/+125
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-04 10:53:29 +0000