| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | x300: Timing changes for the new DAC data interface | Ashish Chaudhari | 2015-03-12 | 1 | -6/+10 |
| | | | | | | | | | | - Switched DAC to DCI delay bypass mode because we shift the DCI in the FPGA now - Changed LMK control to add 900ps delay to DAC clocks to be consistent with the radio_clk delay. The timing analyzer is expecting the two clocks to have a 0 deg phase diff. | ||||
| * | x300: Cleaned up DAC ctrl and clock init logic | Ashish Chaudhari | 2014-11-06 | 1 | -63/+147 |
| | | | | | | | | | | | | - DAC: Squashed configuration into 2 main operations: reset and reset_and_resync - DAC: Put in sleep mode during configuration - DAC: Synchronize only if streaming to more than one DAC - DAC: Use falling edge sync mode - DAC: Fixed power up/down settings - DAC: Frontend sync failure is fatal - Clocks: Refactored clock source change logic - Clocks: Cleaned up init and lock-check sequence | ||||
| * | Merge branch 'maint' | Martin Braun | 2014-09-25 | 1 | -38/+85 |
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| | * | x300: added reset and resync of ADCs and DACs when changing reference clock | michael-west | 2014-09-25 | 1 | -39/+86 |
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| * | | Added missing pure virtual destructors to base classes | Nicholas Corgan | 2014-09-01 | 1 | -1/+5 |
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| * | Merging USRP X300 and X310 support!! | Ben Hilburn | 2014-02-04 | 1 | -0/+146 |
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