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* usrp2: Re-add ability to modulate in the DACMartin Braun2018-03-281-0/+7
| | | | | | | | | | | This partially reverts b29e80cc. That commit fixed a bug with numerical overflows, but also removed the ability to tune using the DAC, effectively reducing the DSP tuning range. This commit allows to tune within +/- 200 MHz using a combination of both the DAC and the DSP tuning in the FPGA. Reviewed-by: Derek Kozek <derek.kozel@ettus.com>
* uhd: Update license headersMartin Braun2018-02-191-1/+2
| | | | | | | All copyright is now attributed to "Ettus Research, a National Instruments company". SPDX headers were also updated to latest version 3.0.
* Move all license headers to SPDX format.Martin Braun2017-12-221-12/+1
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* Added missing pure virtual destructors to base classesNicholas Corgan2014-09-011-1/+3
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* fifo ctrl: spi core work and host implementationJosh Blum2012-03-231-3/+4
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* uhd: update copyright dates on host codeJosh Blum2011-01-131-1/+1
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* uhd: replace all the instances of float not pertaining to io types with ↵Josh Blum2011-01-111-2/+2
| | | | double, simplifies life
* usrp-n: set ad9777 mod mode to transmit above nyquist of DSPJosh Blum2010-12-031-0/+9
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* ADC gain control works.Nick Foster2010-07-281-1/+9
| | | | Separated digital gain and fine gain correction into separate buckets. Changed the rounding policy of gain_group to floor() rather than round().
* Added gain support for USRP2+ ADC.Nick Foster2010-07-271-0/+13
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* Prepend usrp2 onto the helper classes in usrp2 impl to avoid symbol conflicts.Josh Blum2010-06-041-2/+2
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* Added a place for serdes control on the host.Josh Blum2010-05-101-3/+3
| | | | | Fix bug in codec control. Comment out some clock control in fw code.
* Moved adc and dac control into codec control source file.Josh Blum2010-05-101-0/+38
The codec control powers down the chips on destruction.