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- Created AD936x manager class
- Moved functionality from B2x0 and E310 into manager
- Separated property tree + perifs initialization in both device classes
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UHD 3.8.5 increased the TX framesize from 2048 to 4096,
this can lead to issues in 2x2.
The behaviour can avoided by specifying send_frame_size = 2048
for these scenarios.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Conflicts:
fpga-src
host/CMakeLists.txt
host/cmake/Modules/UHDVersion.cmake
host/lib/usrp/b200/b200_impl.hpp
host/lib/usrp/e300/e300_fpga_defs.hpp
host/lib/usrp/x300/x300_fw_common.h
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This was originally limited because it performed poor,
however, with refactoring that has been done since release,
this now gives better performance.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- Master clock rate cannot be less than 10 MHz, which is the
MMCM's minimum operating frequency in the FPGA's capture
interface.
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