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* b200: Fix for PLL setting not being applied intermittentlyAshish Chaudhari2014-12-101-1/+1
| | | | - Made the methods in adf4001_ctrl virtual
* b200: Added variable rate SPI core for AD9361 and ADF4001Ashish Chaudhari2014-08-011-3/+2
| | | | | - Added b200_local_spi core that adjusts the divider when talking to the two chips - AD9361 rate is 1MHz and ADF4001 rate is 10kHz
* uhd: squashed support modules for usrp3 fpga coresJosh Blum2013-07-191-0/+142