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path: root/host/lib/usrp/common/adf4001_ctrl.cpp
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* adf4002: Fixed register programming for power down bitSugandha Gupta2018-04-121-1/+1
| | | | | The bit shift for power down is one off with respect to the ADF4001/ADF4002 data sheet
* uhd: Move internal headers to uhdlib/Martin Braun2018-03-141-2/+2
| | | | | | | | | | | | | | | | To avoid the proliferation of additional include directories and multiple ways of including project-local headers, we now default to moving all headers that are used across UHD into the uhdlib/ subdirectory. Some #include statements were also reordered as they were modified for closer compliance with the coding guidelines. Internal cpp source files should now include files like this: #include <uhdlib/rfnoc/ctrl_iface.hpp> Reviewed-by: Ashish Chaudhari <ashish.chaudhari@ettus.com>
* uhd: Update license headersMartin Braun2018-02-191-1/+2
| | | | | | | All copyright is now attributed to "Ettus Research, a National Instruments company". SPDX headers were also updated to latest version 3.0.
* Move all license headers to SPDX format.Martin Braun2017-12-221-12/+1
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* utils: introduce new logging API and remove msg APIAndrej Rode2017-02-201-1/+1
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* Remove all boost:: namespace prefix for uint32_t, int32_t etc. (fixed-width ↵Martin Braun2016-11-081-30/+30
| | | | | | | | types) - Also removes all references to boost/cstdint.hpp and replaces it with stdint.h (The 'correct' replacement would be <cstdint>, but not all of our compilers support that).
* ADF4002: Fix register programming (bug #974)michael-west2015-12-151-4/+4
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* b200: Added variable rate SPI core for AD9361 and ADF4001Ashish Chaudhari2014-08-011-1/+1
| | | | | - Added b200_local_spi core that adjusts the divider when talking to the two chips - AD9361 rate is 1MHz and ADF4001 rate is 10kHz
* uhd: squashed support modules for usrp3 fpga coresJosh Blum2013-07-191-0/+151