uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	B200/E300: Fix incorrect readback of frequency.	michael-west	2015-05-22	1	-0/+3
\| \| \| \|	When the LO is tuned it changes the frequency on both channels. The frequency value read back for the first channel was not updated when the LO frequency for the other channel was tuned to a different value.
*	ad936x: removing gain_offset from rx set_gain	Jon Kiser	2015-02-11	1	-1/+1
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*	ad9361: rssi readout	Julian Arnold	2015-01-12	1	-1/+5
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*	Added missing pure virtual destructors to base classes	Nicholas Corgan	2014-09-01	1	-1/+16
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*	ad9361: Cleaned up constants and macros	Ashish Chaudhari	2014-08-13	1	-5/+1
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*	ad9361: Converted stdint types to boost types	Ashish Chaudhari	2014-08-12	1	-2/+1
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*	b200, ad9361: Cleanup up AD9361 driver	Ashish Chaudhari	2014-08-12	1	-30/+5
\| \| \| \| \|	- Removed transaction interface - Made the driver a C++ class
*	b200: Moved AD9361 driver to host	Ashish Chaudhari	2014-08-01	1	-48/+31
\| \| \| \| \| \| \|	- Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow
*	b200: changed ad9361 ctrl/transaction magic number 64 to macro, as it is in ↵	Balint Seeber	2014-03-19	1	-7/+9
\| \| \| \|	the FX3 FW
*	b200: throw exception when master clock rate (tick rate) is requested to be ↵	Balint Seeber	2014-02-14	1	-1/+6
\| \| \| \| \| \|	> max for certain # of channels (i.e. restrict to 30.72MHz for MIMO) Also includes sscanf type fix in b200_impl and longer timeout for AD9361 read
*	b200: lower clock rate is 5MHz due to DCM	Josh Blum	2013-08-16	1	-1/+2
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*	b200: use existing query rate calls to clip	Josh Blum	2013-07-19	1	-3/+3
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*	uhd: squashed support modules for usrp3 fpga cores	Josh Blum	2013-07-19	1	-0/+127