| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | b200: Moved AD9361 driver to host | Ashish Chaudhari | 2014-08-01 | 1 | -48/+31 |
| | | | | | | | | - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow | ||||
| * | b200: changed ad9361 ctrl/transaction magic number 64 to macro, as it is in ↵ | Balint Seeber | 2014-03-19 | 1 | -7/+9 |
| | | | | | the FX3 FW | ||||
| * | b200: throw exception when master clock rate (tick rate) is requested to be ↵ | Balint Seeber | 2014-02-14 | 1 | -1/+6 |
| | | | | | | | > max for certain # of channels (i.e. restrict to 30.72MHz for MIMO) Also includes sscanf type fix in b200_impl and longer timeout for AD9361 read | ||||
| * | b200: lower clock rate is 5MHz due to DCM | Josh Blum | 2013-08-16 | 1 | -1/+2 |
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| * | b200: use existing query rate calls to clip | Josh Blum | 2013-07-19 | 1 | -3/+3 |
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| * | uhd: squashed support modules for usrp3 fpga cores | Josh Blum | 2013-07-19 | 1 | -0/+127 |
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index : uhd | |
| Ettus' UHD Repository |
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