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path: root/host/lib/usrp/common/ad9361_ctrl.cpp
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* B200/E300: Fix incorrect readback of frequency.michael-west2015-05-221-0/+9
| | | | When the LO is tuned it changes the frequency on both channels. The frequency value read back for the first channel was not updated when the LO frequency for the other channel was tuned to a different value.
* ad9361: Removed recommended max clock rate warningMartin Braun2015-04-141-7/+1
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* B200: Bug #656. Added FIR coeffs for filters with Fs/4 stop band.Ian Buckley2015-01-191-0/+7
| | | | AD9361 driver can now select coeffs for different interpolation ratios.
* ad9361: rssi readoutJulian Arnold2015-01-121-1/+10
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* ad9361: Made recommended rate a constantMartin Braun2014-09-021-2/+2
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* Added missing pure virtual destructors to base classesNicholas Corgan2014-09-011-1/+14
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* ad9361: Fixed TX direction bug in ad9361_ctrlAshish Chaudhari2014-08-131-1/+1
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* ad9361: Added synchronization to IO and device classesAshish Chaudhari2014-08-131-5/+6
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* ad9361: Converted stdint types to boost typesAshish Chaudhari2014-08-121-20/+20
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* b200, ad9361: Cleanup up AD9361 driverAshish Chaudhari2014-08-121-186/+59
| | | | | - Removed transaction interface - Made the driver a C++ class
* b200: Moved AD9361 driver to hostAshish Chaudhari2014-08-011-33/+171
| | | | | | | - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow
* b200: changed ad9361 read timeout handling (kicks in when requesting ↵Balint Seeber2014-03-191-1/+1
| | | | master_clock_rate above 56MHz)
* uhd: strnlen for platforms w/o itJosh Blum2013-07-251-1/+9
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* b200: use existing query rate calls to clipJosh Blum2013-07-191-2/+2
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* uhd: squashed support modules for usrp3 fpga coresJosh Blum2013-07-191-0/+165