| Commit message (Collapse) | Author | Age | Files | Lines |
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the FX3 FW
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master_clock_rate above 56MHz)
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breaking)
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settings interface.
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> max for certain # of channels (i.e. restrict to 30.72MHz for MIMO)
Also includes sscanf type fix in b200_impl and longer timeout for AD9361 read
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core as subscriber to tick rate change for B200.
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FPGA bump)
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events and expanded packet size to 16k
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