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* Improve LEA-M8F detection and protocol parsingMatthias P. Braendli2015-04-171-5/+3
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* Change GPSDO UART speed back to 115200Matthias P. Braendli2015-04-171-1/+1
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* Improve LEA-M8F autodetection and poll NAV-SOLMatthias P. Braendli2015-04-171-4/+7
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* b200: Bugfix#692: b200_find now returns an empty device vector when hint ↵mcrymble2015-02-061-1/+3
| | | | contains addr0/resource0/etc style keys.
* Merging new UHD_IMAGES_DIR utilities and bug fixes.Ben Hilburn2015-01-272-16/+14
| | | | Also includes NI-USRP Windows Registry Key fixes.
* b200: Added lo_locked sensorMartin Braun2015-01-143-1/+12
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* b200: rssi sensorJulian Arnold2015-01-121-1/+3
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* b200: Fix for PLL setting not being applied intermittentlyAshish Chaudhari2014-12-101-1/+1
| | | | - Made the methods in adf4001_ctrl virtual
* b200: select valid 10 MHz ref (update GPIO) *before* updating ADF4001 ↵Balint Seeber2014-12-081-3/+4
| | | | external ref selection
* b200: serialized access to get_rx/tx_streamJulian Arnold2014-11-212-0/+6
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* MISO and SIMO configurations no longer allowedJulian Arnold2014-10-211-0/+5
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* b200: Bumped FX3 firmware compat number to 7.Ashish Chaudhari2014-10-011-1/+1
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* Merge branch 'maint'Martin Braun2014-09-251-0/+15
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| * B200: added support for reading the exact product name from EEPROM for B200 ↵Neel Pandeya2014-09-251-0/+15
| | | | | | | | and B210
* | Merge branch 'maint'Martin Braun2014-09-231-1/+0
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| * usrp: don't print duplicate GPSDO detection messagesNicholas Corgan2014-09-231-1/+0
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* | b200: Set sensible defaults for freq, gain and rate at startupMartin Braun2014-09-022-5/+19
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* | Merge branch 'master' into ashish/cat_refactor_phase2Ashish Chaudhari2014-08-201-5/+0
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| * | Merge branch 'maint'Martin Braun2014-08-181-5/+0
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| | * - Fixes for channel alignmentmichael-west2014-08-181-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added analog delay for radio clock - Added analog delay for DAC reference clocks - Removed resetting of clock control - Removed setting of reference clock and PPS to external sources during initialization - Fixes for set_time_unknown_pps - Removed wait for PPS edge after setting time from GPSDO - Changed set_time_unknonw_pps to time out based on system time rather than device VITA time
* | | ad9361: Cleaned up constants and macrosAshish Chaudhari2014-08-131-1/+1
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* | | b200, ad9361: Cleanup up AD9361 driverAshish Chaudhari2014-08-122-3/+30
| | | | | | | | | | | | | | | - Removed transaction interface - Made the driver a C++ class
* | | b200: Removed all AD9361 related firmwareAshish Chaudhari2014-08-123-85/+1
|/ / | | | | | | | | | | | | - FX3 does not respond to AD9361 firmware transaction VREQs - FX3 does not respond to AD9361 SPI transaction VREQs - Deleted all AD9361 firmware files - Bumped FW compat to 6
* | Merge branch 'master' into ashish/cat_refactor_masterAshish Chaudhari2014-08-051-0/+5
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| * | Merge branch 'maint'Martin Braun2014-07-311-0/+5
| |\| | | | | | | | | | | | | Conflicts: host/utils/usrp_burn_mb_eeprom.cpp
| | * Merge branch 'maint' into uhd/bug492michael-west2014-07-301-13/+19
| | |\ | | | | | | | | | | | | | | | | Conflicts: host/lib/usrp/b200/b200_impl.cpp
| | * | Fix for BUG #492: UHD: set_time_unknown_pps() fails with GPSDO installedmichael-west2014-06-251-0/+5
| | | | | | | | | | | | | | | | - Added polling for PPS time change after setting time from GPSDO.
* | | | b200: Added variable rate SPI core for AD9361 and ADF4001Ashish Chaudhari2014-08-016-4/+156
| | | | | | | | | | | | | | | | | | | | - Added b200_local_spi core that adjusts the divider when talking to the two chips - AD9361 rate is 1MHz and ADF4001 rate is 10kHz
* | | | b200: Moved AD9361 driver to hostAshish Chaudhari2014-08-014-12/+13
|/ / / | | | | | | | | | | | | | | | | | | - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow
* | / OctoClock firmware upgrade, added host driverNicholas Corgan2014-07-231-1/+2
| |/ |/| | | | | | | | | | | | | | | | | * OctoClock can communicate with UHD over Ethernet * Can read NMEA strings from GPSDO and send to host * Added multi_usrp_clock class for clock devices * uhd::device can now filter to return only USRP devices or clock devices * New OctoClock bootloader can accept firmware download over Ethernet * Added octoclock_burn_eeprom,octoclock_firmware_burner utilities * Added test_clock_synch example to show clock API
* | Merge branch 'origin/b200/bug516' into maintBen Hilburn2014-07-171-4/+4
|\ \ | | | | | | | | | Fixing B200 clock rate float compare.
| * | BUG #516: B210: Fails to Run with 30.72 MHz Clockmichael-west2014-07-101-1/+1
| | | | | | | | | | | | - Addressed feedback from review.
| * | Fix for BUG #516: B210: Fails to Run with 30.72 MHz Clockmichael-west2014-06-181-3/+3
| | | | | | | | | | | | - Corrected clock rate checks for B2x0
| * | Fix for BUG #516: B210: Fails to Run with 30.72 MHz Clockmichael-west2014-06-181-3/+3
| |/ | | | | | | - Corrected clock rate checks for B2x0
* | Merge branch 'origin/b200/bug512' into maintBen Hilburn2014-07-171-9/+15
|\ \ | |/ |/| | | B200 now creates internal PPS. Depends on FPGA change.
| * Enhancement #512: B210: Need an Internal PPSmichael-west2014-06-131-9/+15
| | | | | | | | - Added support for internal PPS selection (set as default)
* | Fix for BUG #500: B210: RX channels are not phase alignedmichael-west2014-06-061-0/+1
|/ | | | - Adding UHD side code to invert second RX channel
* Merge branch 'origin/b200/issue_418'Ben Hilburn2014-04-101-5/+6
|\ | | | | | | Fixing unsafe sscanf call.
| * b100+b200+usrp1: removed potentially unsafe sscanf callMartin Braun2014-04-101-5/+6
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* | b200: Added max link rate infoMartin Braun2014-04-102-1/+4
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* Merge branch adding warning regarding MCR on the B2xx.Ben Hilburn2014-03-274-14/+110
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| * b200: changed ad9361 ctrl/transaction magic number 64 to macro, as it is in ↵Balint Seeber2014-03-191-3/+3
| | | | | | | | the FX3 FW
| * b200: explicitly detect libusb timeoutBalint Seeber2014-03-191-8/+19
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| * b200: changed ad9361 read timeout handling (kicks in when requesting ↵Balint Seeber2014-03-191-3/+10
| | | | | | | | master_clock_rate above 56MHz)
| * b200: addressed review comments (boost::uint16_t & source code long line ↵Balint Seeber2014-03-191-6/+19
| | | | | | | | breaking)
| * Merge branch 'master' of github.com:EttusResearch/uhddev into b200/warn_mimo_mcrBalint Seeber2014-02-201-1/+1
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| * | b200: throw exception when master clock rate (tick rate) is requested to be ↵Balint Seeber2014-02-144-8/+73
| | | | | | | | | | | | | | | | | | > max for certain # of channels (i.e. restrict to 30.72MHz for MIMO) Also includes sscanf type fix in b200_impl and longer timeout for AD9361 read
* | | b200: update FPGA loading percentage every 1% instead of 10%Nicholas Corgan2014-03-271-1/+1
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* | | Pulling in patch from Marcus Leech for includes and older OSes.Ben Hilburn2014-03-261-0/+6
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* | | b200: Added missing include to b200_implMoritz Fischer2014-03-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | * In order to use std::ceil and std::floor, on older compilers we need to still add an include for cmath. Tested-by: Marcus D. Leech <mleech@ripnet.com> Signed-off-by: Moritz Fischer <moritz@ettus.com>
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