| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | b200: Removed all AD9361 related firmware | Ashish Chaudhari | 2014-08-12 | 3 | -85/+1 |
| | | | | | | | | - FX3 does not respond to AD9361 firmware transaction VREQs - FX3 does not respond to AD9361 SPI transaction VREQs - Deleted all AD9361 firmware files - Bumped FW compat to 6 | ||||
| * | Merge branch 'master' into ashish/cat_refactor_master | Ashish Chaudhari | 2014-08-05 | 1 | -0/+5 |
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| | * | Merge branch 'maint' | Martin Braun | 2014-07-31 | 1 | -0/+5 |
| | |\ | | | | | | | | | | | | | Conflicts: host/utils/usrp_burn_mb_eeprom.cpp | ||||
| | | * | Merge branch 'maint' into uhd/bug492 | michael-west | 2014-07-30 | 1 | -13/+19 |
| | | |\ | | | | | | | | | | | | | | | | | Conflicts: host/lib/usrp/b200/b200_impl.cpp | ||||
| | | * | | Fix for BUG #492: UHD: set_time_unknown_pps() fails with GPSDO installed | michael-west | 2014-06-25 | 1 | -0/+5 |
| | | | | | | | | | | | | | | | | | - Added polling for PPS time change after setting time from GPSDO. | ||||
| * | | | | b200: Added variable rate SPI core for AD9361 and ADF4001 | Ashish Chaudhari | 2014-08-01 | 6 | -4/+156 |
| | | | | | | | | | | | | | | | | | | | | | - Added b200_local_spi core that adjusts the divider when talking to the two chips - AD9361 rate is 1MHz and ADF4001 rate is 10kHz | ||||
| * | | | | b200: Moved AD9361 driver to host | Ashish Chaudhari | 2014-08-01 | 4 | -12/+13 |
| |/ / / | | | | | | | | | | | | | | | | | | | - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow | ||||
| * | / | OctoClock firmware upgrade, added host driver | Nicholas Corgan | 2014-07-23 | 1 | -1/+2 |
| | |/ |/| | | | | | | | | | | | | | | | | | * OctoClock can communicate with UHD over Ethernet * Can read NMEA strings from GPSDO and send to host * Added multi_usrp_clock class for clock devices * uhd::device can now filter to return only USRP devices or clock devices * New OctoClock bootloader can accept firmware download over Ethernet * Added octoclock_burn_eeprom,octoclock_firmware_burner utilities * Added test_clock_synch example to show clock API | ||||
| * | | Merge branch 'origin/b200/bug516' into maint | Ben Hilburn | 2014-07-17 | 1 | -4/+4 |
| |\ \ | | | | | | | | | | Fixing B200 clock rate float compare. | ||||
| | * | | BUG #516: B210: Fails to Run with 30.72 MHz Clock | michael-west | 2014-07-10 | 1 | -1/+1 |
| | | | | | | | | | | | | | - Addressed feedback from review. | ||||
| | * | | Fix for BUG #516: B210: Fails to Run with 30.72 MHz Clock | michael-west | 2014-06-18 | 1 | -3/+3 |
| | | | | | | | | | | | | | - Corrected clock rate checks for B2x0 | ||||
| | * | | Fix for BUG #516: B210: Fails to Run with 30.72 MHz Clock | michael-west | 2014-06-18 | 1 | -3/+3 |
| | |/ | | | | | | | - Corrected clock rate checks for B2x0 | ||||
| * | | Merge branch 'origin/b200/bug512' into maint | Ben Hilburn | 2014-07-17 | 1 | -9/+15 |
| |\ \ | |/ |/| | | | B200 now creates internal PPS. Depends on FPGA change. | ||||
| | * | Enhancement #512: B210: Need an Internal PPS | michael-west | 2014-06-13 | 1 | -9/+15 |
| | | | | | | | | | - Added support for internal PPS selection (set as default) | ||||
| * | | Fix for BUG #500: B210: RX channels are not phase aligned | michael-west | 2014-06-06 | 1 | -0/+1 |
| |/ | | | | - Adding UHD side code to invert second RX channel | ||||
| * | Merge branch 'origin/b200/issue_418' | Ben Hilburn | 2014-04-10 | 1 | -5/+6 |
| |\ | | | | | | | Fixing unsafe sscanf call. | ||||
| | * | b100+b200+usrp1: removed potentially unsafe sscanf call | Martin Braun | 2014-04-10 | 1 | -5/+6 |
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| * | | b200: Added max link rate info | Martin Braun | 2014-04-10 | 2 | -1/+4 |
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| * | Merge branch adding warning regarding MCR on the B2xx. | Ben Hilburn | 2014-03-27 | 4 | -14/+110 |
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| | * | b200: changed ad9361 ctrl/transaction magic number 64 to macro, as it is in ↵ | Balint Seeber | 2014-03-19 | 1 | -3/+3 |
| | | | | | | | | | the FX3 FW | ||||
| | * | b200: explicitly detect libusb timeout | Balint Seeber | 2014-03-19 | 1 | -8/+19 |
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| | * | b200: changed ad9361 read timeout handling (kicks in when requesting ↵ | Balint Seeber | 2014-03-19 | 1 | -3/+10 |
| | | | | | | | | | master_clock_rate above 56MHz) | ||||
| | * | b200: addressed review comments (boost::uint16_t & source code long line ↵ | Balint Seeber | 2014-03-19 | 1 | -6/+19 |
| | | | | | | | | | breaking) | ||||
| | * | Merge branch 'master' of github.com:EttusResearch/uhddev into b200/warn_mimo_mcr | Balint Seeber | 2014-02-20 | 1 | -1/+1 |
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| | * | | b200: throw exception when master clock rate (tick rate) is requested to be ↵ | Balint Seeber | 2014-02-14 | 4 | -8/+73 |
| | | | | | | | | | | | | | | | | | | | > max for certain # of channels (i.e. restrict to 30.72MHz for MIMO) Also includes sscanf type fix in b200_impl and longer timeout for AD9361 read | ||||
| * | | | b200: update FPGA loading percentage every 1% instead of 10% | Nicholas Corgan | 2014-03-27 | 1 | -1/+1 |
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| * | | | Pulling in patch from Marcus Leech for includes and older OSes. | Ben Hilburn | 2014-03-26 | 1 | -0/+6 |
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| * | | | b200: Added missing include to b200_impl | Moritz Fischer | 2014-03-23 | 1 | -0/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | * In order to use std::ceil and std::floor, on older compilers we need to still add an include for cmath. Tested-by: Marcus D. Leech <mleech@ripnet.com> Signed-off-by: Moritz Fischer <moritz@ettus.com> | ||||
| * | | | b200: Added channel mapping capabilities | Martin Braun | 2014-02-25 | 3 | -47/+42 |
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| * | | b200: Fixed bug in rx_dsp_core_3000 that would assume 3 halfbands and X300 ↵ | Ashish Chaudhari | 2014-02-19 | 1 | -1/+1 |
| |/ | | | | settings interface. | ||||
| * | Merging USRP X300 and X310 support!! | Ben Hilburn | 2014-02-04 | 2 | -14/+8 |
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| * | Added timed control commands to test_timed_commands example. Added radio ↵ | Michael West | 2014-01-15 | 1 | -0/+2 |
| | | | | | core as subscriber to tick rate change for B200. | ||||
| * | Merging mwest's improvements to B2xx utility. | Ben Hilburn | 2013-12-11 | 2 | -0/+25 |
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| * | Merge of mwest's fix to the sse2_fc32_to_sc16 converter. | Ben Hilburn | 2013-12-11 | 1 | -18/+19 |
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| * | lib: fixed use of -> to . after switching parameter from pointer to reference | Nicholas Corgan | 2013-12-03 | 1 | -1/+1 |
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| * | Final merge of Balint's 'kitchen_sink' B200 fixes. | Ben Hilburn | 2013-11-27 | 3 | -83/+177 |
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| * | Squashed merge of Coverity fixes. | Ben Hilburn | 2013-11-27 | 1 | -4/+13 |
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| * | b200: fix loopback transfer timeout when operating at USB2release_003_006_001 | Balint Seeber | 2013-11-20 | 1 | -1/+2 |
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| * | b200: check return value from control write of FPGA bitstream for short transferrelease_003_006_000 | Balint Seeber | 2013-11-19 | 1 | -0/+2 |
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| * | b200: extra check on loopback request to determine VREQ transfer size | Balint Seeber | 2013-11-19 | 1 | -0/+2 |
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| * | b200: auto-select VREQ xfer size regardless of FW version | Balint Seeber | 2013-11-19 | 1 | -5/+13 |
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| * | Merge branch 'bug182' | Nicholas Corgan | 2013-11-19 | 4 | -13/+28 |
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| | * | More cleanup for dynamic linking. | Michael West | 2013-11-18 | 1 | -1/+1 |
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| | * | BUG #182: Cleaned up for proper dynamic linking of libuhd. | Michael West | 2013-11-18 | 2 | -6/+6 |
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| | * | BUG #182: Refactored b2xx_fx3_utils to use files from UHD | Michael West | 2013-11-15 | 3 | -8/+23 |
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| * | | b200: Reverted RX SPP 2044 -> 2000 (unresolved issue with one app, wait for ↵ | Balint Seeber | 2013-11-19 | 1 | -1/+1 |
| | | | | | | | | | FPGA bump) | ||||
| * | | Merge remote-tracking branch 'origin/b200/dtor-master' into b200/kitchen_sink | Balint Seeber | 2013-11-19 | 3 | -10/+28 |
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| | * | | b200/dtor-stall: final fixes for stall bug | Johannes Demel | 2013-11-19 | 1 | -4/+5 |
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| | * | | b200/dtor-stall: fixed bug that stalled b200 on shutdown. | Johannes Demel | 2013-11-19 | 3 | -9/+26 |
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| * | | b200: increase FPGA VREQ transfer size to 512 if operating over USB3 | Balint Seeber | 2013-11-19 | 1 | -3/+17 |
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