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path: root/host/lib/usrp/b200/b200_impl.hpp
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* b200: Removed all AD9361 related firmwareAshish Chaudhari2014-08-121-1/+1
| | | | | | | - FX3 does not respond to AD9361 firmware transaction VREQs - FX3 does not respond to AD9361 SPI transaction VREQs - Deleted all AD9361 firmware files - Bumped FW compat to 6
* b200: Added variable rate SPI core for AD9361 and ADF4001Ashish Chaudhari2014-08-011-1/+2
| | | | | - Added b200_local_spi core that adjusts the divider when talking to the two chips - AD9361 rate is 1MHz and ADF4001 rate is 10kHz
* b200: Moved AD9361 driver to hostAshish Chaudhari2014-08-011-2/+2
| | | | | | | - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow
* b200: Added max link rate infoMartin Braun2014-04-101-1/+3
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* Merge branch adding warning regarding MCR on the B2xx.Ben Hilburn2014-03-271-4/+7
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| * b200: throw exception when master clock rate (tick rate) is requested to be ↵Balint Seeber2014-02-141-4/+7
| | | | | | | | | | | | > max for certain # of channels (i.e. restrict to 30.72MHz for MIMO) Also includes sscanf type fix in b200_impl and longer timeout for AD9361 read
* | b200: Added channel mapping capabilitiesMartin Braun2014-02-251-4/+7
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* Merging USRP X300 and X310 support!!Ben Hilburn2014-02-041-10/+4
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* Final merge of Balint's 'kitchen_sink' B200 fixes.Ben Hilburn2013-11-271-2/+2
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* Merge branch 'bug182'Nicholas Corgan2013-11-191-4/+0
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| * BUG #182: Cleaned up for proper dynamic linking of libuhd.Michael West2013-11-181-4/+0
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* | b200/dtor-stall: fixed bug that stalled b200 on shutdown.Johannes Demel2013-11-191-2/+2
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* uhd: wb_iface is now a public interfaceJosh Blum2013-10-041-2/+2
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* b200: firmware update changed for FPGA load workBen Hilburn2013-09-101-1/+1
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* b200: changed for pps select registerJosh Blum2013-08-131-1/+1
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* b200: squashed support for b200 onto master branchJosh Blum2013-07-191-0/+196