| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
| |
|
|
|
|
|
| |
This uses the new b100/e100 common core and FIFO control modules.
Subsequent commit will be the compatible FPGA merge.
|
|
|
|
| |
the current host code and places them in the images directory
|
| |
|
|
|
|
| |
dboard subdev names are more descriptive (RFX RX is now RFX1200 RX, etc)
|
|
|
|
| |
"stuffing zeroes" problem and improves transport reliability.
|
|
|
|
| |
Must zero out the default IQ correction to have zero effect by default.
|
| |
|
| |
|
|
|
|
|
|
| |
Determine state of control endpoint,
re-enumerate to put in a known state,
rerun some initialization code.
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
|
|
|
| |
git log
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
|
|
|
| |
look for devices if you like
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|