| Commit message (Collapse) | Author | Age | Files | Lines |
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Replaced with initialization lists.
Note: uhd::dict does not work with initializer lists without making
changes to said data structure. This commit has no functional changes,
so keeping the boost::assigns for uhd::dict.
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Replace with std::this_thread::sleep_for().
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Updated the following blocks and components: Radio, DmaFIFO,
block_ctrl_base and node_ctrl_base, blockdef_xml_impl, device3_impl.
No functional changes.
- Demoted some log messages
- Consistent log style (use unique_id())
- Some adaptation of coding style where close to log statements
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When doing a NUM_SAMPS_AND_DONE stream command, there is a limit to the
number of samples that can be requested (as of now, there's 28 bits for
this counter). When the number was exceeded, the previous error message
was not helpful.
Note that the DDC block will multiply the number of requested samples by
the decimation rate. This means the number of samples requested from the
radio is higher than the number of samples requested by the application.
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- Bump compat number for DDC/DUC to 2.0
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- ctrl_iface is now longer a wb_iface. All it can do now is send command
packets, and receive responses to those.
- ctrl_iface does not store command time or tick rate
- wb_iface_adapter is no longer a set of functors, but a wrapper around
ctrl_iface. Command times are stored once, in the block.
- DMA FIFO and radio block controllers have an easier time getting
access to a timed_wb_iface
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Before, we were calling peeks with the number of the readback register.
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To avoid the proliferation of additional include directories and
multiple ways of including project-local headers, we now default to
moving all headers that are used across UHD into the uhdlib/
subdirectory.
Some #include statements were also reordered as they were modified for
closer compliance with the coding guidelines.
Internal cpp source files should now include files like this:
#include <uhdlib/rfnoc/ctrl_iface.hpp>
Reviewed-by: Ashish Chaudhari <ashish.chaudhari@ettus.com>
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This change will allow legacy compat connect any in/out ports
radios/ddcs/ducs/dmafifo block connect together in a legacy graph:
[HOST]=>DFIFO/SFIFO=>DUC=>RADIO=>DDC=>[HOST]
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Some log statements were incorrectly using multi-line log statements.
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All copyright is now attributed to "Ettus Research, a National
Instruments company".
SPDX headers were also updated to latest version 3.0.
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Replace with lambdas.
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- New file: uhdlib/utils/math.hpp
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- Applied changes to DUC and DDC blocks
- Fixed minor formatting
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- Replaces some very verbose boost::bind() with simpler lambdas
- Replaces some boost:tuple with std::tuple
- Replaces some Boost locks with std locks
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This reverts commit c8cdbfc4d4e307017e02dd48c449d3e3f38118af.
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Thanks to github user mdmikh for pointing out problem and fix.
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We need more radio index and radio slot for N310.
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skip_dram is used
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- NUM_HALFBANDS and CIC_MAX are no longer hard coded and are now
readback regs.
- both DDC and DUC use same encoding to enable halfbands
(increment the number)
- removed hacky hack & fixed get_output_rate/get_input_rate
to include only valid rates based on NUM_HALFBANDS and CIC_MAX.
- added compatibility number readback w/ warning/error messages
- Updated images package to include new DDC/DUC (affects X-Series only)
- Updated fpga-src submodule pointer
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Also added stubs in the default impl.
Reviewed-By: Ashish Chaudhari <ashish@ettus.com>
Reviewed-By: Derek Kozel <derek.kozel@ettus.com>
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It's feasible that error messages are sent out during overrun handling,
which would cause a nested invocation of handle_overrun(). This adds a
lock to prevent that.
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The ctrl_iface class will assume that a response packet is available.
There are cases where no response packet is available, in which case
sequence numbers should not get popped from the stack prematurely.
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The file was missing a .cpp suffix for the dma_fifo_block_ctrl_impl
file, somehow CMake was being smart and inferring the filetype.
Be explicit.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Loopback FIFOs ("SRAM FIFOs") only have a single channel, unlike the
DRAM FIFOs (and that's also the reason why we have full bandwdith
between all channels using those). We thus need to ensure that every TX
stream gets its own SRAM FIFO.
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Default implementations simply throw an exception. Makes it easier to
write new radio controls that do not implement GPIO features.
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