| Commit message (Collapse) | Author | Age | Files | Lines |
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- Set SPI clock back to 3 MHz
- Fix returned frequency for ADF5355 (rev A and B boards)
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- Added delay for VTUNE calibration as per ADF5355 and ADF5356 data sheets
- Increased SPI clock to 10 MHz
- Removed write to register 10 during tuning of ADF5356 to match ADF5355 code and reduce tune time
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EEPROM
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- If FRAC2 isn't exactly FRAC1 at certain frequencies, drifting spurs can
be seen in the spectrum
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- Add default parser helper
- Allow _enforce_discrete() for str_arg
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- The flushing mechanism now looks similar to that in noc_shell
- Make use of new flush bit in FIFO control register
- Restrict using the clear bit only after flushing to ensure no
partial packets are introduced in the stream. (clear immediately
empties out FIFOs)
- Changes are backwards compatible with older FPGAs
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This device is the only one using it, and no one will ever use it going
forward.
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Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
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This disables the ability to do "network mode" on the E310.
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Since the frequency shifter is set to a relative rate, it needs to be
updated when changing the sampling rate.
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LVDS interface can support both timing modes 1R1T/2R2T
The API sets the required bit in catalina registers.
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Replace with std::this_thread::sleep_for().
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Allows full bandwidth range to user.
Reviewed-by: Michael West <michael.west@ettus.com>
Reviewed-by: Martin Braun <martin.braun@ettus.com>
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- Remove all use of boost::bind and boost::function
- Demote some log messages to DEBUG
- Change some formatting to match coding guidelines
- B2xx/E310: Match changes in loopback function
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- Bump compat number for DDC/DUC to 2.0
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Note: This tool is not considered done, complete, unchangeable, or
anything other than experimental.
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- ctrl_iface is now longer a wb_iface. All it can do now is send command
packets, and receive responses to those.
- ctrl_iface does not store command time or tick rate
- wb_iface_adapter is no longer a set of functors, but a wrapper around
ctrl_iface. Command times are stored once, in the block.
- DMA FIFO and radio block controllers have an easier time getting
access to a timed_wb_iface
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Before, we were calling peeks with the number of the readback register.
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To avoid the proliferation of additional include directories and
multiple ways of including project-local headers, we now default to
moving all headers that are used across UHD into the uhdlib/
subdirectory.
Some #include statements were also reordered as they were modified for
closer compliance with the coding guidelines.
Internal cpp source files should now include files like this:
#include <uhdlib/rfnoc/ctrl_iface.hpp>
Reviewed-by: Ashish Chaudhari <ashish.chaudhari@ettus.com>
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Reviewed-by: Trung Tran <trung.tran@ettus.com>
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This defines and reads configuration files that can be used to customize
UHD's behaviour. On Unix systems, they default to:
/etc/uhd/uhd.conf
$APPDATA/.uhd/uhd.conf
On Windows systems, it will look in:
%ProgramData%/uhd/uhd.conf
%AppData%/.uhd/uhd.conf
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All copyright is now attributed to "Ettus Research, a National
Instruments company".
SPDX headers were also updated to latest version 3.0.
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- New file: uhdlib/utils/math.hpp
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- Applied changes to DUC and DDC blocks
- Fixed minor formatting
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This class is not publicly exported. It is meant to read config files in
the INI format.
Reviewed-by: Brent Stapleton <brent.stapleton@ettus.com>
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- Allow enums to be non-consecutive
- Move to uhdlib/
- Add unit tests
- Updated N230 use of constrained_device_args_t
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Reviewed-by: Ashish Chaudhari <ashish.chaudhari@ettus.com>
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