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* usrp-e-crc-rw : Work with GU fpga image. Cleaned up warnings.Philip Balister2011-02-211-13/+24
* usrp-e-mm-loopback : Works with GU fpga image. Cleaned up warnings.Philip Balister2011-02-211-8/+21
* Add back line that mysteriously disappeared. I blame the cat.Philip Balister2011-02-161-0/+1
* usrp-e-timed test program. Add checks for packet length and sequencePhilip Balister2011-02-161-0/+12
* usrp-e-crc-rw: Fix data rate calculation.Philip Balister2011-02-151-14/+37
* usrp-e100: Check in wip for timed image test program.Philip Balister2011-02-141-14/+37
* Fix typo in usage message.Philip Balister2011-02-081-1/+1
* Fixes for timed fpga interface test program. Still need to solve the CRCPhilip Balister2011-02-011-1/+3
* Start converting the timed test program to work with mmap interface.Philip Balister2011-01-261-8/+17
* Update header from in e100 test programs from main uhd.Philip Balister2011-01-261-5/+6
* Mark received block as accepted by user space.Philip Balister2011-01-261-0/+2
* Update timed crc test program to use mmap's interface. Needs testing.Philip Balister2011-01-251-53/+77
* usrp_e: Add driver compatibility ioctl to header file.Philip Balister2010-10-211-0/+3
* Ignore direction for GPIO 114 since it is always an input.root2010-09-301-9/+11
* Use a dummy write to start DMA transfers when sending data to the FPGA.Philip Balister2010-09-211-1/+1
* Use the ring buffer sizes read from the kernel.Philip Balister2010-09-211-3/+3
* Convert write to use the mmap interface.Philip Balister2010-09-211-4/+22
* Read the ring buffer size from the kernel and use that to set up thePhilip Balister2010-09-212-28/+34
* Fix ring buffer size calculation.Philip Balister2010-09-211-4/+4
* Fix really dumb mistake in rad ring buffer code. Add/comment debugroot2010-09-201-4/+6
* Convert to use mmaped rx ring buffer.Philip Balister2010-08-111-13/+50
* Convert non-mmaped loopback test program to use new simple read/write api.Philip Balister2010-08-111-43/+33
* Add usrp-e-mm-loopback to .gitignore.Philip Balister2010-08-111-0/+1
* Loopback test now supports variable size and works with mmapable ring buffer.Philip Balister2010-08-113-12/+227
* Add gitignore file.Philip Balister2010-06-151-0/+19
* Rename loopback of random length packets test program so we know it needsPhilip Balister2010-06-132-2/+2
* Exit on errors. Run until an error occurs. Alloq for up to 2 sequencePhilip Balister2010-06-131-6/+17
* Update usrp_e.h file. Change programs to use struct element status instead of...Philip Balister2010-06-136-20/+29
* reverted usrp-e-led sorryJosh Blum2010-05-281-8/+8
* Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_eJosh Blum2010-05-271-8/+8
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* | Divide by 4 to convert byts/sec to samples/sec. Multiply by 4 is right out.Philip Balister2010-05-231-1/+1
* | Work on crc testing program. Currently dumps first received packet to thePhilip Balister2010-05-211-10/+36
* | OK, now crc uses the timed interface to set the data rate.Philip Balister2010-05-211-21/+21
* | Rename loopback test program to match bin file name.Philip Balister2010-05-202-3/+3
* | Enable realtime scheduling in loopback test to prevent overruns.Philip Balister2010-05-201-0/+5
* | Display data rate in samples/second and fix typo.Philip Balister2010-05-191-5/+5
* | Calculate received sample rate for loopback test.Philip Balister2010-05-191-3/+24
* | Use better optimization settings.Philip Balister2010-05-191-5/+6
* | Fix initialization bug.Philip Balister2010-05-191-0/+6
* | Rename test program to match FPGA bin file name and add data rate calculation.Philip Balister2010-05-192-19/+39
* | Keep repo in sync with my churn ...Philip Balister2010-05-192-7/+12
* | Comment out progress indicators.Philip Balister2010-05-181-4/+8
* | Revert "Revert "Update test program to reflect what is in the FPGA image.""Philip Balister2010-05-181-21/+20
* | Remove rand for now. Fix bug in data rate calculation.Philip Balister2010-05-181-2/+4
* | Revert "Update test program to reflect what is in the FPGA image."Philip Balister2010-05-181-20/+21
* | Update test program to reflect what is in the FPGA image.Philip Balister2010-05-141-21/+20
* | got clock gen config working and testedJosh Blum2010-05-131-4/+6
* | Connect enable to the correct gpio.Philip Balister2010-05-131-1/+1
* | Change to 24 bit transfers.Philip Balister2010-05-131-2/+2
* | Print a . for every packet received.Philip Balister2010-05-132-0/+5
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