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* Start converting the timed test program to work with mmap interface.Philip Balister2011-01-261-8/+17
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* Update header from in e100 test programs from main uhd.Philip Balister2011-01-261-5/+6
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* Mark received block as accepted by user space.Philip Balister2011-01-261-0/+2
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* Update timed crc test program to use mmap's interface. Needs testing.Philip Balister2011-01-251-53/+77
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* usrp_e: Add driver compatibility ioctl to header file.Philip Balister2010-10-211-0/+3
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* Ignore direction for GPIO 114 since it is always an input.root2010-09-301-9/+11
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* Use a dummy write to start DMA transfers when sending data to the FPGA.Philip Balister2010-09-211-1/+1
| | | | Poll will also start data transfers.
* Use the ring buffer sizes read from the kernel.Philip Balister2010-09-211-3/+3
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* Convert write to use the mmap interface.Philip Balister2010-09-211-4/+22
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* Read the ring buffer size from the kernel and use that to set up thePhilip Balister2010-09-212-28/+34
| | | | structures that read and write the ring buffer.
* Fix ring buffer size calculation.Philip Balister2010-09-211-4/+4
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* Fix really dumb mistake in rad ring buffer code. Add/comment debugroot2010-09-201-4/+6
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* Convert to use mmaped rx ring buffer.Philip Balister2010-08-111-13/+50
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* Convert non-mmaped loopback test program to use new simple read/write api.Philip Balister2010-08-111-43/+33
| | | | | Done by copying from the -mm version, which will be used to test mmaped ring buffer.
* Add usrp-e-mm-loopback to .gitignore.Philip Balister2010-08-111-0/+1
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* Loopback test now supports variable size and works with mmapable ring buffer.Philip Balister2010-08-113-12/+227
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* Add gitignore file.Philip Balister2010-06-151-0/+19
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* Rename loopback of random length packets test program so we know it needsPhilip Balister2010-06-132-2/+2
| | | | loopback fpga image. Needs debug.
* Exit on errors. Run until an error occurs. Alloq for up to 2 sequencePhilip Balister2010-06-131-6/+17
| | | | number errors so program can start with "dirty" fpga contents.
* Update usrp_e.h file. Change programs to use struct element status instead ↵Philip Balister2010-06-136-20/+29
| | | | of flags.
* reverted usrp-e-led sorryJosh Blum2010-05-281-8/+8
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* Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_eJosh Blum2010-05-271-8/+8
|\ | | | | | | | | Conflicts: host/utils/CMakeLists.txt
* | Divide by 4 to convert byts/sec to samples/sec. Multiply by 4 is right out.Philip Balister2010-05-231-1/+1
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* | Work on crc testing program. Currently dumps first received packet to thePhilip Balister2010-05-211-10/+36
| | | | | | | | screen. Started to reduce teh number of warnings.
* | OK, now crc uses the timed interface to set the data rate.Philip Balister2010-05-211-21/+21
| | | | | | | | | | | | | | | | | | | | Revert "Revert "Revert "Update test program to reflect what is in the FPGA image.""" This reverts commit b5dfe74e991d240f0e666dfd521726ec61128eb8. Conflicts: host/apps/omap_debug/usrp-e-crc-rw.c
* | Rename loopback test program to match bin file name.Philip Balister2010-05-202-3/+3
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* | Enable realtime scheduling in loopback test to prevent overruns.Philip Balister2010-05-201-0/+5
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* | Display data rate in samples/second and fix typo.Philip Balister2010-05-191-5/+5
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* | Calculate received sample rate for loopback test.Philip Balister2010-05-191-3/+24
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* | Use better optimization settings.Philip Balister2010-05-191-5/+6
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* | Fix initialization bug.Philip Balister2010-05-191-0/+6
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* | Rename test program to match FPGA bin file name and add data rate calculation.Philip Balister2010-05-192-19/+39
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* | Keep repo in sync with my churn ...Philip Balister2010-05-192-7/+12
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* | Comment out progress indicators.Philip Balister2010-05-181-4/+8
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* | Revert "Revert "Update test program to reflect what is in the FPGA image.""Philip Balister2010-05-181-21/+20
| | | | | | | | | | | | This reverts commit 7d0a98fc33c17457c9f4cd8e03eddb0d559457f0. Must make filenames more different.
* | Remove rand for now. Fix bug in data rate calculation.Philip Balister2010-05-181-2/+4
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* | Revert "Update test program to reflect what is in the FPGA image."Philip Balister2010-05-181-20/+21
| | | | | | | | | | | | This reverts commit 4d82cabe938b398bc42cab3d316983d2bbe40d06. Now sure where I got the idea this image did not contain the rate setting code.
* | Update test program to reflect what is in the FPGA image.Philip Balister2010-05-141-21/+20
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* | got clock gen config working and testedJosh Blum2010-05-131-4/+6
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* | Connect enable to the correct gpio.Philip Balister2010-05-131-1/+1
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* | Change to 24 bit transfers.Philip Balister2010-05-131-2/+2
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* | Print a . for every packet received.Philip Balister2010-05-132-0/+5
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* | Add calculation for data trasnfer rates.Philip Balister2010-05-121-3/+43
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* | Add program to do initial configuration of the clkgen chip.Philip Balister2010-05-102-1/+298
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* | Update usrp_e.h file from kernel header.Philip Balister2010-05-071-5/+0
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* | First pass at data transfer program that uses CRC.Philip Balister2010-05-072-1/+200
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* | Print an error and exit if open fails for some programs.Philip Balister2010-05-073-0/+17
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* | Remove workaround for driver hang.root2010-05-053-6/+2
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* | Spi data returned in struct now.Philip Balister2010-05-031-1/+1
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* | Update path to put module in.Philip Balister2010-05-031-1/+1
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