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path: root/host/apps/omap_debug/usrp-e-crc-rw.c
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* usrp-e-utils : Remove old files.Philip Balister2011-02-211-379/+0
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* usrp-e-crc-rw : Work with GU fpga image. Cleaned up warnings.Philip Balister2011-02-211-13/+24
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* Add back line that mysteriously disappeared. I blame the cat.Philip Balister2011-02-161-0/+1
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* usrp-e-timed test program. Add checks for packet length and sequencePhilip Balister2011-02-161-0/+12
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* usrp-e-crc-rw: Fix data rate calculation.Philip Balister2011-02-151-14/+37
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* usrp-e100: Check in wip for timed image test program.Philip Balister2011-02-141-14/+37
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* Fix typo in usage message.Philip Balister2011-02-081-1/+1
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* Fixes for timed fpga interface test program. Still need to solve the CRCPhilip Balister2011-02-011-1/+3
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* Start converting the timed test program to work with mmap interface.Philip Balister2011-01-261-8/+17
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* Update timed crc test program to use mmap's interface. Needs testing.Philip Balister2011-01-251-53/+77
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* Update usrp_e.h file. Change programs to use struct element status instead ↵Philip Balister2010-06-131-4/+11
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* Work on crc testing program. Currently dumps first received packet to thePhilip Balister2010-05-211-10/+36
| | | | screen. Started to reduce teh number of warnings.
* OK, now crc uses the timed interface to set the data rate.Philip Balister2010-05-211-21/+21
| | | | | | | | | | Revert "Revert "Revert "Update test program to reflect what is in the FPGA image.""" This reverts commit b5dfe74e991d240f0e666dfd521726ec61128eb8. Conflicts: host/apps/omap_debug/usrp-e-crc-rw.c
* Keep repo in sync with my churn ...Philip Balister2010-05-191-1/+2
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* Comment out progress indicators.Philip Balister2010-05-181-4/+8
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* Revert "Revert "Update test program to reflect what is in the FPGA image.""Philip Balister2010-05-181-21/+20
| | | | | | This reverts commit 7d0a98fc33c17457c9f4cd8e03eddb0d559457f0. Must make filenames more different.
* Remove rand for now. Fix bug in data rate calculation.Philip Balister2010-05-181-2/+4
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* Revert "Update test program to reflect what is in the FPGA image."Philip Balister2010-05-181-20/+21
| | | | | | This reverts commit 4d82cabe938b398bc42cab3d316983d2bbe40d06. Now sure where I got the idea this image did not contain the rate setting code.
* Update test program to reflect what is in the FPGA image.Philip Balister2010-05-141-21/+20
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* Add calculation for data trasnfer rates.Philip Balister2010-05-121-3/+43
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* First pass at data transfer program that uses CRC.Philip Balister2010-05-071-0/+195