aboutsummaryrefslogtreecommitdiffstats
path: root/fpga
Commit message (Expand)AuthorAgeFilesLines
...
* fpga: lib: add pause support to ethernet xportAndrew Moch2021-06-036-7/+112
* fpga: lib: Add eth_ipv4_internalWade Fife2021-06-032-0/+442
* fpga: lib: Add zynquplus family to axi_bitqHumberto Jimenez2021-06-031-12/+13
* fpga: tools: Add ability to run commands before routeWade Fife2021-06-031-5/+11
* fpga: tools: Add ability to patch IP during generationWade Fife2021-06-032-0/+87
* fpga: tools: Add support for RFSoCHumberto Jimenez2021-06-032-9/+9
* fpga: lib: Minor cleanup of axi_lite.vhLars Amsel2021-06-031-2/+23
* fpga: rfnoc: Add ability to disable output flow controlWade Fife2021-04-142-7/+22
* fpga: lib: Add rx_front_end_gen3 testbenchWade Fife2021-04-092-0/+247
* fpga: lib: Update round_sd to eliminate X from simulationWade Fife2021-04-091-14/+45
* fpga: lib: Fix simulation of axi_fir_filterWade Fife2021-04-091-1/+1
* TwinRX: Remove frontend filtermichael-west2021-04-081-59/+8
* fpga: docs: Improve documentation of rx_frontend_gen3Martin Braun2021-04-071-1/+73
* fpga: lib: Fix DDS_SIN_COS_LUT outputs in makefilePaul Butler2021-03-311-1/+1
* fpga: dsp: Fix formatting of rx_dcoffset and add docsMartin Braun2021-03-091-38/+110
* fpga: Remove Python2 support from build systemMartin Braun2021-01-0417-119/+121
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-114-358/+541
* fpga: lib: add glitch free mux moduleMax Köhler2020-12-032-0/+30
* fpga: e31x: Add OOT sources to Makefile.e31x.incWade Fife2020-11-131-0/+8
* fpga: lib: Fix axis_strm_monitor parametersWade Fife2020-10-201-2/+2
* fpga: lib: Fix small packets stuck in 10 GbE TXAndrew Moch2020-10-051-3/+17
* fpga: lib: Fix 10 GbE cut-through modeAndrew Moch2020-09-161-4/+16
* fpga: lib: add generic to disable bitq engine tri-statingMax Köhler2020-09-162-11/+16
* fpga: docs: Update user manual for UHD 4.0Wade Fife2020-09-1111-542/+1042
* fpga: e31x: Change image file to e310_rfnoc_image_coreWade Fife2020-09-093-5/+5
* E320: Revert addition of Replay blockmichael-west2020-09-043-266/+270
* fpga: Added AA image mappings to N320Aaron Rossetto2020-09-031-1/+6
* fpga: Add Replay Block to RFNoC Core Imagemattprost2020-09-0320-591/+2586
* fpga: Update DRAM IO signaturesWade Fife2020-09-034-28/+28
* fpga: sim: chdr_stream_endpoint_tb improvementsWade Fife2020-08-312-36/+150
* fpga: sim: Fix stream command and status modelsWade Fife2020-08-311-9/+9
* fpga: n3xx: Update AXI interconnect address rangeWade Fife2020-08-284-2928/+2217
* fpga: e320: Update AXI interconnect address rangeWade Fife2020-08-282-2195/+1373
* fpga: rfnoc: Update CHDR stream INIT commandWade Fife2020-08-281-3/+10
* fpga: lib: Fix lint warningsWade Fife2020-08-283-3/+3
* fpga: rfnoc: Remove deprecated filesWade Fife2020-08-2323-2679/+5
* fpga: Update coding guidelinesWade Fife2020-08-201-30/+107
* fpga: e31x: Change RFNoC Ctrl clock to 40 MHzWade Fife2020-08-192-1/+3
* fpga: e320: Fix timeout for timekeeper registersWade Fife2020-08-191-191/+284
* fpga: n3xx: Fix timeout for timekeeper registersWade Fife2020-08-193-195/+307
* fpga: e31x: Fix timeout for timekeeper registersWade Fife2020-08-191-180/+278
* fpga: lib: Add more CtrlPort constantsWade Fife2020-08-191-7/+12
* fpga: lib: Add ctrlport_to_regport bridgeWade Fife2020-08-192-0/+91
* fpga: e320: Fix default YAML target to E320_1GMartin Braun2020-08-171-1/+1
* fpga: e310: Fix device in image core YAMLWade Fife2020-08-141-1/+1
* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
* fpga: lib: Fix SWITCH_ON_LAST in axi_mux_selectWade Fife2020-08-131-18/+39
* fpga: lib: add handshake to replace FIFO for ctrlport CDCMax Köhler2020-08-133-48/+143
* n320: Double radio ingress buffer sizemattprost2020-08-122-8/+8
* fpga: rfnoc: Fix clock crossing in axis_data_to_chdrWade Fife2020-08-121-69/+89
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-30 23:19:33 +0000