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* fpga: x400: Set DRAM speed to 2.0 GT/sWade Fife2022-02-071-26/+26
* fpga: x400: Add axi_inter_4x64_512_bd IPWade Fife2022-02-073-0/+604
* fpga: x400: Add axi_inter_2x128_512_bd IPWade Fife2022-02-073-0/+449
* images: Update N32x CPLD manifestHumberto Jimenez2022-01-311-1/+1
* fpga: docs: Add B205mini FPGA infoWade Fife2022-01-281-9/+11
* fpga: n3xx: rh: cpld: Refactor CPLD build processHumberto Jimenez2022-01-256-24/+119
* fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svhMartin Braun2022-01-256-1058/+1
* fpga: x400: cpld: Bump copyrightJavier Valenzuela2022-01-259-9/+9
* fpga: x400: Bump copyrightJavier Valenzuela2022-01-2514-14/+14
* fpga: x400: Expand PS GPIO port for DIO controlJavier Valenzuela2022-01-257-19/+58
* fpga: x400: Add SPI bus support for GPIO portsJavier Valenzuela2022-01-259-60/+1338
* fpga: x400: Add GPIO control via ATR and DB stateJavier Valenzuela2022-01-2514-199/+2932
* fpga: x400: Connect Radio Blocks to DIOJavier Valenzuela2022-01-2511-232/+627
* fpga: tools: Fix adding directories for HDL sourceWade Fife2022-01-131-1/+1
* fpga: hls: Add version to generated HLS IPWade Fife2022-01-131-2/+2
* fpga: x400: Fix rfnoc_image_core.vh pathWade Fife2022-01-121-1/+1
* uhd: update git://github.com references to httpsSteven Koo2022-01-113-13/+13
* fpga: e320: Connect CTRL_IN pins to FPGAMartin Braun2022-01-102-1/+12
* fpga: e320: Remove copy/paste from N310 codeMartin Braun2022-01-101-9/+0
* images: Add the utilization report for X410 images (X4_200)Martin Braun2021-12-171-1/+3
* fpga: x300: Fix time register readbackWade Fife2021-12-151-2/+2
* fpga: usrp2: update build tools to use python3Matthew Crymble2021-12-082-6/+6
* fpga: tools: Update Vivado scripts to use python3Wade Fife2021-12-081-4/+4
* rfnoc: Fix noc_shell direction commentsWade Fife2021-12-0818-81/+86
* fpga: x300: OR ATR signals going into db_controlMartin Braun2021-12-071-1/+10
* fpga: x400: cpld: Add manufacturing supportHumberto Jimenez2021-12-014-7/+27
* fpga: x400: Refactor CPLDs build processHumberto Jimenez2021-12-0134-258/+741
* fpga: tools: Add Quartus build utilitiesHumberto Jimenez2021-12-013-0/+163
* fpga: Add ability to get time from Radio blockmichael-west2021-11-173-2/+26
* fpga: rfnoc: Add RFNoC CHDR resize moduleWade Fife2021-11-047-0/+2031
* fpga: rfnoc: Add CHDR management util functionsWade Fife2021-11-041-4/+85
* x410: correct 100GbE link speedAndrew Lynch2021-11-022-2/+2
* fpga: lib: Clean up axi_muxWade Fife2021-10-281-91/+160
* fpga: rfnoc: Add labels to axi_switch generate blocksWade Fife2021-10-281-36/+67
* fpga: rfnoc: Add labels to chdr_mgmt_pkt_handlerWade Fife2021-10-281-30/+45
* fpga: rfnoc: Add documentation to chdr_xb_routing_tableWade Fife2021-10-281-46/+84
* fpga: Shorten line length for Launchpad linterAaron Rossetto2021-10-281-2/+4
* siggen: Fix direction of rotationWade Fife2021-10-274-35/+44
* fpga: x300: Update synchronizer constraintWade Fife2021-09-131-1/+1
* fpga: n3xx: Update synchronizer constraintWade Fife2021-09-131-3/+2
* fpga: lib: Update example constraint in synchronizerWade Fife2021-09-131-18/+40
* fpga: Update help message for setupenv.shWade Fife2021-09-101-5/+7
* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-09-088-16/+8
* fpga: tools: Add UHD_FPGA_DIR definition to synthesisWade Fife2021-09-083-6/+11
* fpga: Set default part for sim in setupenv.shWade Fife2021-08-306-5/+24
* x300: Fix sfpp_io_core tuser widthWade Fife2021-08-271-1/+1
* fpga: Fix Xilinx bitfile parser for Python 3Martin Braun2021-08-241-31/+54
* sim: Update chdr_16sc_to_sc12 testbenchmichael-west2021-08-101-137/+159
* fpga: Re-order error and data packetsmichael-west2021-08-101-2/+28
* fpga: Fix sc16 to sc12 convertermichael-west2021-08-101-62/+80
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