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* fpga: lib: Fix small packets stuck in 10 GbE TXAndrew Moch2020-10-051-3/+17
* fpga: lib: Fix 10 GbE cut-through modeAndrew Moch2020-09-161-4/+16
* fpga: lib: add generic to disable bitq engine tri-statingMax Köhler2020-09-162-11/+16
* fpga: docs: Update user manual for UHD 4.0Wade Fife2020-09-1111-542/+1042
* fpga: e31x: Change image file to e310_rfnoc_image_coreWade Fife2020-09-093-5/+5
* E320: Revert addition of Replay blockmichael-west2020-09-043-266/+270
* fpga: Added AA image mappings to N320Aaron Rossetto2020-09-031-1/+6
* fpga: Add Replay Block to RFNoC Core Imagemattprost2020-09-0320-591/+2586
* fpga: Update DRAM IO signaturesWade Fife2020-09-034-28/+28
* fpga: sim: chdr_stream_endpoint_tb improvementsWade Fife2020-08-312-36/+150
* fpga: sim: Fix stream command and status modelsWade Fife2020-08-311-9/+9
* fpga: n3xx: Update AXI interconnect address rangeWade Fife2020-08-284-2928/+2217
* fpga: e320: Update AXI interconnect address rangeWade Fife2020-08-282-2195/+1373
* fpga: rfnoc: Update CHDR stream INIT commandWade Fife2020-08-281-3/+10
* fpga: lib: Fix lint warningsWade Fife2020-08-283-3/+3
* fpga: rfnoc: Remove deprecated filesWade Fife2020-08-2323-2679/+5
* fpga: Update coding guidelinesWade Fife2020-08-201-30/+107
* fpga: e31x: Change RFNoC Ctrl clock to 40 MHzWade Fife2020-08-192-1/+3
* fpga: e320: Fix timeout for timekeeper registersWade Fife2020-08-191-191/+284
* fpga: n3xx: Fix timeout for timekeeper registersWade Fife2020-08-193-195/+307
* fpga: e31x: Fix timeout for timekeeper registersWade Fife2020-08-191-180/+278
* fpga: lib: Add more CtrlPort constantsWade Fife2020-08-191-7/+12
* fpga: lib: Add ctrlport_to_regport bridgeWade Fife2020-08-192-0/+91
* fpga: e320: Fix default YAML target to E320_1GMartin Braun2020-08-171-1/+1
* fpga: e310: Fix device in image core YAMLWade Fife2020-08-141-1/+1
* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
* fpga: lib: Fix SWITCH_ON_LAST in axi_mux_selectWade Fife2020-08-131-18/+39
* fpga: lib: add handshake to replace FIFO for ctrlport CDCMax Köhler2020-08-133-48/+143
* n320: Double radio ingress buffer sizemattprost2020-08-122-8/+8
* fpga: rfnoc: Fix clock crossing in axis_data_to_chdrWade Fife2020-08-121-69/+89
* fpga: lib: Change max FFT size to 1024Wade Fife2020-08-111-2/+2
* fpga: rfnoc: Add tests to FFT blockWade Fife2020-08-102-39/+202
* fpga: lib: add Intel MAX10 architecture for 2clk FIFOMax Köhler2020-08-062-28/+33
* fpga: lib: Update xport_svAndrew Moch2020-08-056-182/+437
* fpga: rfnoc: Add RFNoC Keep One in N blockAaron Rossetto2020-08-057-0/+1432
* fpga: rfnoc: Add RFNoC Replay blockWade Fife2020-08-0411-875/+4101
* fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ramWade Fife2020-08-041-0/+12
* fpga: rfnoc: Add support for CHDR_W < ITEM_W*NIPCWade Fife2020-08-042-137/+195
* fpga: lib: Fix comments and indentation in axi_fifo_short.vWade Fife2020-08-041-98/+87
* fpga: n320: Add BIST (AA) image filessteviez2020-07-315-0/+1148
* fpga: lib: Add xge features for new xport_svAndrew Moch2020-07-311-100/+191
* fpga: sim: Update PkgEthernetAndrew Moch2020-07-311-57/+91
* fpga: sim: Fix AxiLiteBfmAndrew Moch2020-07-311-3/+3
* fpga: lib: Update AxiLiteIfAndrew Moch2020-07-311-1/+74
* fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64Andrew Moch2020-07-301-1/+1
* fpga: tools: RESOLVE_PATH checks for an empty pathAndrew Moch2020-07-301-4/+4
* fpga: rfnoc: Add Signal Generator RFNoC blockWade Fife2020-07-3012-18/+1925
* fpga: lib: Add axis_packetize moduleWade Fife2020-07-302-0/+162
* fpga: Add Switchboard RFNoC blockJesse Zhang2020-07-307-0/+1121
* fpga, mpm: Bump FPGA compat numberRobertWalstab2020-07-243-3/+3
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