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* fpga: rfnoc: Make Replay packet length independent of burst sizeWade Fife2022-03-092-106/+158
| | | | | | | | | | | | | Before this change, the packet size output by the Replay block during playback was limited to length of a full memory burst transaction. This led to relatively small packets during playback (typically 2 KiB) and had other side effects, such as simultaneous playback from two different memory locations using different packet sizes because of differences in memory alignment. With this change, the configured packet size, as set by the register REG_PLAY_WORDS_PER_PKT, is used for all packets except the last packet of playback, which can of course be smaller.
* fgpa: rfnoc: Set Replay memory transactions to 2 KiBWade Fife2022-03-092-7/+15
| | | | | | | This sets the Replay block's counter width so that memory bursts are up to 2 KiB. Previously, the counter width was fixed, which meant that wide memories would require especially large buffers and could exceed the 4 KiB limit imposed by AXI.
* fpga: Add SPDX license identifierAaron Rossetto2022-03-091-0/+2
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* fpga: x400: Cleanup FPGA MakefileWade Fife2022-03-041-40/+61
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* fpga: x400: Add support for DRAM with 400 MHz BWWade Fife2022-03-042-22/+24
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* fpga: x400: Change AXI XB for DRAM to 512-bitWade Fife2022-03-041-106/+17
| | | | | | Change the width of the crossbar in the AXI Interconnect IP from 256-bit to 512-bit to match the DRAM memory controller width and to give better performance.
* fpga: rfnoc: Fix strobe probability in radio simulatorWade Fife2022-03-041-7/+7
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* fpga: rfnoc: Regenerate noc_shellsWade Fife2022-03-0418-29/+47
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* fpga: x400: Add SPI Controller Info registerJavier Valenzuela2022-03-046-11/+156
| | | | | | Include a register that contains SPI controller information. Currently, it only provides the number of slaves addressable by the SPI engine.
* fpga: x400: Adjust SPI engine strobes alignmentJavier Valenzuela2022-03-044-9/+14
| | | | | | Modify behavior of clock crossing between radio_clk and radio_clk_2x. This ensures strobe signals are always asserted for a single radio_clk_2x cycle and when radio_clk is low.
* fpga: x400: Set replay SEP buffers to twice MTUWade Fife2022-02-242-8/+8
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* fpga: Add SPDX license identifierAaron Rossetto2022-02-231-0/+2
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* Remove FSRU-related filesMartin Braun2022-02-221-1/+0
| | | | | | | The FSRU (aka EISCAT) was never supported in UHD 4.0. The FPGA repository never had the relevant files, and the block controller also never existed. This removes all the corresponding files from MPM, as well as some references from makefiles.
* fpga: e320: Add DRAM portsWade Fife2022-02-181-97/+97
| | | | | This adds two additional ports to the DRAM, for a total of up to four channels connected to DRAM.
* images: Remove references to N230Martin Braun2022-02-151-7/+0
| | | | | | USRP N230 is no longer supported starting with UHD 4, and thus, we can remove it from the image manifest. This will no longer download N230 images when calling uhd_images_downloader from UHD 4.
* fpga: n3xx: Fix DRAM FIFO address alignmentWade Fife2022-02-103-6/+6
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* fpga: rfnoc: Change AWIDTH default for axi_ram_fifoWade Fife2022-02-101-1/+1
| | | | | Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs assume the AXI address width is the same as MEM_ADDR_W.
* fpga: e31x: Add DRAM supportWade Fife2022-02-1015-99/+1499
| | | | | | | | | This adds DRAM support to E31x devices. Due to the size of the DDR3 memory controller, it is not enabled by default. You can include the memory controller IP in the build by adding the DRAM environment variable to your build. For example: DRAM=1 make E310_SG3
* fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parametersJonathon Pendlum2022-02-103-11/+20
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* fpga: x400: Add DRAM enable macroJavier Valenzuela2022-02-101-0/+4
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* images: Add utilization report files to B2xx image filesMartin Braun2022-02-101-4/+8
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* fpga: b2xx: Generate utilization report filesMartin Braun2022-02-102-18/+24
| | | | | | | | | | | | Currently, the build process copies the .twr and .syr files into the build/ process after running ISE. For a succinct utilization report, those files are not suitable, though, because they contain too much information. However, the build process already produces a custom, short utilization report using grep and a summary of those reports. This patch modifies the build such that the same output is copied into a usrp_$product_fpga.rpt file, similar to our gen-3 devices.
* fpga: x400: zbx: cpld: Bump ZBX regmap copyrightJavier Valenzuela2022-02-1011-11/+11
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* fpga: x400: cpld: Bump CMI wrapper copyrightJavier Valenzuela2022-02-102-2/+2
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* fpga: ci: Increase PR pipeline timeoutWade Fife2022-02-071-3/+3
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* fpga: x400: Bump minor versionWade Fife2022-02-073-8/+8
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* fpga: x400: Update rfnoc_image_core filesWade Fife2022-02-078-98/+1327
| | | | | Updates the RFNoC image core files to include DRAM and default image changes.
* fpga: x400: Add Replay to 100 and 200 MHz imagesWade Fife2022-02-072-36/+107
| | | | | This adds the RFNoC replay block to the defautl 100 and 200 MHz images for X410.
* fpga: x400: Add DRAM supportWade Fife2022-02-075-106/+1272
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* fpga: x400: Set DRAM speed to 2.0 GT/sWade Fife2022-02-071-26/+26
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* fpga: x400: Add axi_inter_4x64_512_bd IPWade Fife2022-02-073-0/+604
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* fpga: x400: Add axi_inter_2x128_512_bd IPWade Fife2022-02-073-0/+449
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* images: Update N32x CPLD manifestHumberto Jimenez2022-01-311-1/+1
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* fpga: docs: Add B205mini FPGA infoWade Fife2022-01-281-9/+11
| | | | | | - Add ISE WebPACK supported FPGAs - Add FPGA type for B205mini - Update product name and URL for Vivado
* fpga: n3xx: rh: cpld: Refactor CPLD build processHumberto Jimenez2022-01-256-24/+119
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* fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svhMartin Braun2022-01-256-1058/+1
| | | | | Both files are a UHD 3 remnant and potentially confusing for UHD 4 codebase readers.
* fpga: x400: cpld: Bump copyrightJavier Valenzuela2022-01-259-9/+9
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* fpga: x400: Bump copyrightJavier Valenzuela2022-01-2514-14/+14
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* fpga: x400: Expand PS GPIO port for DIO controlJavier Valenzuela2022-01-257-19/+58
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* fpga: x400: Add SPI bus support for GPIO portsJavier Valenzuela2022-01-259-60/+1338
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* fpga: x400: Add GPIO control via ATR and DB stateJavier Valenzuela2022-01-2514-199/+2932
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* fpga: x400: Connect Radio Blocks to DIOJavier Valenzuela2022-01-2511-232/+627
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* fpga: tools: Fix adding directories for HDL sourceWade Fife2022-01-131-1/+1
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* fpga: hls: Add version to generated HLS IPWade Fife2022-01-131-2/+2
| | | | | | | | | This change causes HLS IP to be exported with a version of 1.0.0 instead of a date code. Due to a bug in Vivado, date codes after 0x7FFFFFFF (anything in 2022 or beyond) cause an error. Setting an explicit revision avoids this issue. See Xilinx AR 76960 for details.
* fpga: x400: Fix rfnoc_image_core.vh pathWade Fife2022-01-121-1/+1
| | | | | | Previously, when running rfnoc_image_builder, the rfnoc_image_core.vh file in the main x400 directory was being used instead of the one generated by rfnoc_image_builder.
* uhd: update git://github.com references to httpsSteven Koo2022-01-113-13/+13
| | | | | | | GitHub is removing support for using git://. Switch to https. https://github.blog/2021-09-01-improving-git-protocol-security-github/ Signed-off-by: Steven Koo <steven.koo@ni.com>
* fpga: e320: Connect CTRL_IN pins to FPGAMartin Braun2022-01-102-1/+12
| | | | | | | | These pins control hardware-controlled fast-lock for tuning or cycle-accurate gain control. This commit does nothing to these pins other than expose them into the design and assign them to zero. This does not change the current behaviour (the motherboard has pull-downs on these pins, so they're low by default).
* fpga: e320: Remove copy/paste from N310 codeMartin Braun2022-01-101-9/+0
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* images: Add the utilization report for X410 images (X4_200)Martin Braun2021-12-171-1/+3
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* fpga: x300: Fix time register readbackWade Fife2021-12-151-2/+2
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