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* fpga: remove liberioRobertWalstab2020-07-204-127/+3
* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-209-89/+68
* fpga: e31x: Add gitignore fileMartin Braun2020-07-181-0/+8
* e31x: Minor cleanup on top-level e31x.v moduleMartin Braun2020-07-182-15/+14
* e31x: Swap out liberio for internal ethernet in the idle imageRobertWalstab2020-07-181-2/+2
* e31x: fpga: connect device_idRobertWalstab2020-07-181-1/+5
* fpga: rfnoc: Add RFNoC Moving Average blockWade Fife2020-07-168-0/+1587
* n32x: Swap out liberio for internal EthernetRobertWalstab2020-07-161-30/+138
* n3xx: Swap out liberio for internal EthernetRobertWalstab2020-07-164-1115/+1262
* e31x: Swap out liberio for internal EthernetRobertWalstab2020-07-165-429/+522
* e320: Swap out liberio for internal EthernetAlex Williams2020-07-164-520/+532
* fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntaxMax Köhler2020-07-101-39/+41
* fpga: n3xx: Fix White Rabbit imagesWade Fife2020-07-011-3/+19
* fpga: lib: Add width agnostic version of Ethernet InterfaceAndrew Moch2020-06-3014-0/+3340
* fpga: rfnoc: Add Log-Power blockWade Fife2020-06-296-0/+1006
* fpga: rfnoc: Fix chdr_update_length functionWade Fife2020-06-291-1/+1
* fpga: rfnoc: Add RFNoC Window blockWade Fife2020-06-298-0/+1454
* fpga: tools: Highlight suppressible errors from vlintWade Fife2020-06-291-1/+1
* fpga: lib: Fix axi_packet_gate RAM dib widthWade Fife2020-06-291-1/+1
* fpga: lib: Add features to axi_lite.vhAndrew Moch2020-06-261-23/+62
* fpga: lib: Add synthesizable AXI4-Stream SV componentsAndrew Moch2020-06-2520-78/+4195
* fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tbWade Fife2020-06-251-8/+16
* fpga: lib: Add interface and model for AXI4-LiteAndrew Moch2020-06-246-1/+1099
* fpga: lib: Pipeline and add clken to ip_hdr_checksumAndrew Moch2020-06-244-66/+51
* fpga: tools: Fix ModelSim return statusWade Fife2020-06-182-5/+12
* fpga: rfnoc: Add support for 512-bit CHDR widthsAndrew Moch2020-06-1819-389/+568
* fpga: lib: add extended spi core for 64bitMax Köhler2020-06-172-0/+287
* fpga: tools: remove temporary Xilinx directories for BD recreationMax Köhler2020-06-151-10/+13
* fpga: Update RFNOC_EDGE_TBL_FILE for CygwinWade Fife2020-06-124-4/+4
* fpga: tools: Allow multiple top modules with ModelSimWade Fife2020-06-111-1/+1
* fpga: lib: extend wb_spi ability to limit transmission lengthMax Köhler2020-06-041-3/+9
* fpga: lib: Fix writes in axil_regport_masterAndrew Moch2020-06-041-23/+43
* fpga: rfnoc: Add defaults for rate changingWade Fife2020-05-282-10/+14
* fpga: tools: Improve detection of setupenv sourcingWade Fife2020-05-281-29/+31
* fpga: rfnoc: Add RFNoC Add/Sub blockWade Fife2020-05-287-10/+1190
* fpga: sim: Add packet_info_equal functionWade Fife2020-05-283-1/+15
* rfnoc: Add Split Stream RFNoC blockWade Fife2020-05-286-0/+932
* fpga: tools: Improve native ModelSim supportWade Fife2020-05-263-72/+255
* fpga: tools: Add contents of directories for HDL sourceWade Fife2020-05-263-5/+26
* fpga: rfnoc: Add Vector IIR RFNoC blockWade Fife2020-05-198-20/+1394
* fpga: tools: Remove uhd_image_builderMartin Braun2020-05-184-1244/+0
* x300: Expand DRAM address space to 1GWade Fife2020-05-181-3/+3
* fpga: e31x: Replace symbolic link for CygwinWade Fife2020-05-121-1/+1
* fpga: tools: Fix HLS IP build with CygwinHumberto Jimenez2020-05-122-4/+10
* fpga: rfnoc: Clean up ctrlport_splitter usageWade Fife2020-05-122-2/+2
* fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1Wade Fife2020-05-121-45/+61
* TwinRX: Remove decimation from frontendMichael West2020-05-121-36/+52
* DUC/DDC: Add variable time incrementMichael West2020-05-125-19/+39
* X300: Make VITA time monotonicMichael West2020-05-121-2/+2
* fpga: Change default MTU to 10Wade Fife2020-05-115-5/+5
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