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* fpga: e31x: Change RFNoC Ctrl clock to 40 MHzWade Fife2020-08-192-1/+3
* fpga: e320: Fix timeout for timekeeper registersWade Fife2020-08-191-191/+284
* fpga: n3xx: Fix timeout for timekeeper registersWade Fife2020-08-193-195/+307
* fpga: e31x: Fix timeout for timekeeper registersWade Fife2020-08-191-180/+278
* fpga: lib: Add more CtrlPort constantsWade Fife2020-08-191-7/+12
* fpga: lib: Add ctrlport_to_regport bridgeWade Fife2020-08-192-0/+91
* fpga: e320: Fix default YAML target to E320_1GMartin Braun2020-08-171-1/+1
* fpga: e310: Fix device in image core YAMLWade Fife2020-08-141-1/+1
* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
* fpga: lib: Fix SWITCH_ON_LAST in axi_mux_selectWade Fife2020-08-131-18/+39
* fpga: lib: add handshake to replace FIFO for ctrlport CDCMax Köhler2020-08-133-48/+143
* n320: Double radio ingress buffer sizemattprost2020-08-122-8/+8
* fpga: rfnoc: Fix clock crossing in axis_data_to_chdrWade Fife2020-08-121-69/+89
* fpga: lib: Change max FFT size to 1024Wade Fife2020-08-111-2/+2
* fpga: rfnoc: Add tests to FFT blockWade Fife2020-08-102-39/+202
* fpga: lib: add Intel MAX10 architecture for 2clk FIFOMax Köhler2020-08-062-28/+33
* fpga: lib: Update xport_svAndrew Moch2020-08-056-182/+437
* fpga: rfnoc: Add RFNoC Keep One in N blockAaron Rossetto2020-08-057-0/+1432
* fpga: rfnoc: Add RFNoC Replay blockWade Fife2020-08-0411-875/+4101
* fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ramWade Fife2020-08-041-0/+12
* fpga: rfnoc: Add support for CHDR_W < ITEM_W*NIPCWade Fife2020-08-042-137/+195
* fpga: lib: Fix comments and indentation in axi_fifo_short.vWade Fife2020-08-041-98/+87
* fpga: n320: Add BIST (AA) image filessteviez2020-07-315-0/+1148
* fpga: lib: Add xge features for new xport_svAndrew Moch2020-07-311-100/+191
* fpga: sim: Update PkgEthernetAndrew Moch2020-07-311-57/+91
* fpga: sim: Fix AxiLiteBfmAndrew Moch2020-07-311-3/+3
* fpga: lib: Update AxiLiteIfAndrew Moch2020-07-311-1/+74
* fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64Andrew Moch2020-07-301-1/+1
* fpga: tools: RESOLVE_PATH checks for an empty pathAndrew Moch2020-07-301-4/+4
* fpga: rfnoc: Add Signal Generator RFNoC blockWade Fife2020-07-3012-18/+1925
* fpga: lib: Add axis_packetize moduleWade Fife2020-07-302-0/+162
* fpga: Add Switchboard RFNoC blockJesse Zhang2020-07-307-0/+1121
* fpga, mpm: Bump FPGA compat numberRobertWalstab2020-07-243-3/+3
* TwinRX: Fix increased noise floormichael-west2020-07-211-1/+1
* fpga: remove liberioRobertWalstab2020-07-204-127/+3
* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-209-89/+68
* fpga: e31x: Add gitignore fileMartin Braun2020-07-181-0/+8
* e31x: Minor cleanup on top-level e31x.v moduleMartin Braun2020-07-182-15/+14
* e31x: Swap out liberio for internal ethernet in the idle imageRobertWalstab2020-07-181-2/+2
* e31x: fpga: connect device_idRobertWalstab2020-07-181-1/+5
* fpga: rfnoc: Add RFNoC Moving Average blockWade Fife2020-07-168-0/+1587
* n32x: Swap out liberio for internal EthernetRobertWalstab2020-07-161-30/+138
* n3xx: Swap out liberio for internal EthernetRobertWalstab2020-07-164-1115/+1262
* e31x: Swap out liberio for internal EthernetRobertWalstab2020-07-165-429/+522
* e320: Swap out liberio for internal EthernetAlex Williams2020-07-164-520/+532
* fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntaxMax Köhler2020-07-101-39/+41
* fpga: n3xx: Fix White Rabbit imagesWade Fife2020-07-011-3/+19
* fpga: lib: Add width agnostic version of Ethernet InterfaceAndrew Moch2020-06-3014-0/+3340
* fpga: rfnoc: Add Log-Power blockWade Fife2020-06-296-0/+1006
* fpga: rfnoc: Fix chdr_update_length functionWade Fife2020-06-291-1/+1
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