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* fpga: Remove Python2 support from build systemMartin Braun2021-01-0417-119/+121
| | | | | | | - 2to3 was used to convert the Python scripts, except where the tool choked and manual intervention was required - All references to "python" where replaced with "python3" - buffer() was replaced by memoryview()
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-114-358/+541
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* fpga: lib: add glitch free mux moduleMax Köhler2020-12-032-0/+30
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* fpga: e31x: Add OOT sources to Makefile.e31x.incWade Fife2020-11-131-0/+8
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* fpga: lib: Fix axis_strm_monitor parametersWade Fife2020-10-201-2/+2
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* fpga: lib: Fix small packets stuck in 10 GbE TXAndrew Moch2020-10-051-3/+17
| | | | | | Any packet less than CUT_THROUGH bytes has a high chance of getting stuck in the TX FIFO of the xge_mac_wrapper. In cut-through mode we were waiting for CUT_THROUGH bytes before transmitting the packet.
* fpga: lib: Fix 10 GbE cut-through modeAndrew Moch2020-09-161-4/+16
| | | | | | | When operating in cut-through mode the hold off from the MAC was not applying back pressure, so when the TX interface filled up, data was dropped. This bug was introduced when cut-through was added, and does not impact the original implementation.
* fpga: lib: add generic to disable bitq engine tri-statingMax Köhler2020-09-162-11/+16
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* fpga: docs: Update user manual for UHD 4.0Wade Fife2020-09-1111-542/+1042
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* fpga: e31x: Change image file to e310_rfnoc_image_coreWade Fife2020-09-093-5/+5
| | | | | | | This renames e31x_rfnoc_image_core.* to e310_rfnoc_image_core.*. This makes the naming consistent with the rest of the build process (which uses "e310" for all variants of e31x) and fixes an issue in which the wrong file name was used by rfnoc_image_builder.
* E320: Revert addition of Replay blockmichael-west2020-09-043-266/+270
| | | | | | The DMA FIFO is needed for DDR3 BIST, so it is being restored for now. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: Added AA image mappings to N320Aaron Rossetto2020-09-031-1/+6
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* fpga: Add Replay Block to RFNoC Core Imagemattprost2020-09-0320-591/+2586
| | | | | | | | Add the Replay RFNoC block to the RFNoC core image for x300, x310, n300, n310, n320/n321, and e320. The Replay block is contained within its own static connection, so previous default behavior is still supported. Signed-off-by: mattprost <matt.prost@ni.com>
* fpga: Update DRAM IO signaturesWade Fife2020-09-034-28/+28
| | | | | | | | This updates the IO signatures so that all devices and RFNoC blocks use the same IO signature for the DRAM. This is needed because the IO signatures must match between the RFNoC blocks and the devices. This means that some devices have extra bits in the IO signature for the address, but the extra bits will simply be ignored.
* fpga: sim: chdr_stream_endpoint_tb improvementsWade Fife2020-08-312-36/+150
| | | | | | | - Adds test coverage for stream command and status packets - Cleans up report output during simulation - Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can be run directly instead of just chdr_stream_endpoint_all_tb
* fpga: sim: Fix stream command and status modelsWade Fife2020-08-311-9/+9
| | | | | | | | This updates PkgChdrBfm to correct some errors when modeling stream command and stream status packets. - Fix behavior when CHDR_W = 512 - Fix assertions in read_ctrl()
* fpga: n3xx: Update AXI interconnect address rangeWade Fife2020-08-284-2928/+2217
| | | | | This change allows the entire 2 GiB address space to be accessed on each memory port.
* fpga: e320: Update AXI interconnect address rangeWade Fife2020-08-282-2195/+1373
| | | | | This change allows the entire 2 GiB address space to be accessed on each memory port.
* fpga: rfnoc: Update CHDR stream INIT commandWade Fife2020-08-281-3/+10
| | | | | | This changes the behavior of the stream command with the INIT OpCode such that sending the command with 0 for the values causes no flow control stream status packets to be sent in response to incoming data.
* fpga: lib: Fix lint warningsWade Fife2020-08-283-3/+3
| | | | | Fixes various synthesis/simulation warnings that were being generated due to incorrectly sized constants.
* fpga: rfnoc: Remove deprecated filesWade Fife2020-08-2323-2679/+5
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* fpga: Update coding guidelinesWade Fife2020-08-201-30/+107
| | | | | | | | | | - Update recommended header - Update module examples - Add file/naming guidelines for modules - Add default_nettype recommendation - Add guidelines for generate statements - Recommend all caps for constants - Misc typos and adjustments
* fpga: e31x: Change RFNoC Ctrl clock to 40 MHzWade Fife2020-08-192-1/+3
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* fpga: e320: Fix timeout for timekeeper registersWade Fife2020-08-191-191/+284
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: n3xx: Fix timeout for timekeeper registersWade Fife2020-08-193-195/+307
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: e31x: Fix timeout for timekeeper registersWade Fife2020-08-191-180/+278
| | | | | | | | Fixing an issue in which a very slow radio_clk (due to low sample clock rate) could cause bus transactions to be issued to the timekeeper faster than it could service them, resulting in a timeout. This change replaces RegPort with CtrlPort so that proper flow control can be maintained to the timekeeper.
* fpga: lib: Add more CtrlPort constantsWade Fife2020-08-191-7/+12
| | | | Add some missing CtrlPort signal widths to ctrlport.vh.
* fpga: lib: Add ctrlport_to_regport bridgeWade Fife2020-08-192-0/+91
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* fpga: e320: Fix default YAML target to E320_1GMartin Braun2020-08-171-1/+1
| | | | | It was set to E320_HG, which is not a valid target, causing build errors unless -t E320_1G was provided to rfnoc_image_builder.
* fpga: e310: Fix device in image core YAMLWade Fife2020-08-141-1/+1
| | | | | Device was set to e31x, but this is not a valid device type. All e31x devices use the e310 device type.
* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
| | | | | This change prevents packets from being chopped midway if the switchboard configuration is changed when a packet is in flight.
* fpga: lib: Fix SWITCH_ON_LAST in axi_mux_selectWade Fife2020-08-131-18/+39
| | | | | Thange allows the mux to switch cleanly between packets, if the mux select input is changed while a packet is in flight.
* fpga: lib: add handshake to replace FIFO for ctrlport CDCMax Köhler2020-08-133-48/+143
| | | | | | | | The clock crossing of the ctrlport used FIFOs to transfer requests and responses between clock domains. This commit adds a handshake based on the pulse synchronizer to reduce the resource usage for ctrlport clock domain crossing. Data is stored in a single register while the pulse synchronizer handles the signaling of valid flags.
* n320: Double radio ingress buffer sizemattprost2020-08-122-8/+8
| | | | | | | This increases the size of the ingress buffers for the N320 radio to support 250MHz TX streaming rates. Signed-off-by: mattprost <matt.prost@ni.com>
* fpga: rfnoc: Fix clock crossing in axis_data_to_chdrWade Fife2020-08-121-69/+89
| | | | | | | | | This fixes some incorrectly handled clock crossings from axis_data_clk to axis_chdr_clk, which could have manifested as timing failures (on E320) or incorrect behavior, depending on the product and noc_shell configuration. Also cleans up trailing white space.
* fpga: lib: Change max FFT size to 1024Wade Fife2020-08-111-2/+2
| | | | | | | | | | | | | The max FFT size was 4096, but we don't currently have any devices that can do that without modification. This is because, currently, the FFT size must be the same as the packet size, and the largest packet size supported by most devices is about 8000 bytes, or 2000 sc16 samples. Therefore, the largest FFT size supported without modifying other code is 1024 samples. This change frees up about 21% of the LUTs and 36% of the BRAM used by axi_fft and makes the software block controller and the IP agree on the maximum FFT size.
* fpga: rfnoc: Add tests to FFT blockWade Fife2020-08-102-39/+202
| | | | | This adds additional tests to the testbench to cover register reads and basic IFFT functionaltiy.
* fpga: lib: add Intel MAX10 architecture for 2clk FIFOMax Köhler2020-08-062-28/+33
| | | | | | | | | | | | | This commit derives parameters for MAX10 devices if provided by the DEVICE parameter. MAX10 devices FIFO generator support up to 36 bit wide FIFOs using embedded memory (M9K) in simple dual port mode, which is treated equally to RAM in the parameters. In combination with sorting the ctrlport signals by usage, the used resources can be reduced on the MAX10 devices from 6 to 3 M9K blocks for a ctrlport_clk_cross instance without time and portids.
* fpga: lib: Update xport_svAndrew Moch2020-08-056-182/+437
| | | | | | | | | - Detect dropped words at the dispatch level. This prevents an overflow on CHDR from block CPU. - Dropped packets are recorded as CPU or CHDR drop count - Refactor to put chdr_xport_adapter.sv in different clock domain to improve timing - Unwrinkle tkeep/trailing transitions
* fpga: rfnoc: Add RFNoC Keep One in N blockAaron Rossetto2020-08-057-0/+1432
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* fpga: rfnoc: Add RFNoC Replay blockWade Fife2020-08-0411-875/+4101
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* fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ramWade Fife2020-08-041-0/+12
| | | | | Adding a check for bursts that cross the 4 KiB boundary to the AXI4 memory model. Crossing a 4 KiB boundary is not allowed by AXI4.
* fpga: rfnoc: Add support for CHDR_W < ITEM_W*NIPCWade Fife2020-08-042-137/+195
| | | | | | | | | This change fixes the case where CHDR_W < ITEM_W*NIPC. It also adds a state machine to stall the input to the pyld_fifo to ensure that the pkt_info_fifo will not overflow. Previously in some cases it allowed the same word to be inserted into the pyld_fifo multiple times.
* fpga: lib: Fix comments and indentation in axi_fifo_short.vWade Fife2020-08-041-98/+87
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* fpga: n320: Add BIST (AA) image filessteviez2020-07-315-0/+1148
| | | | | | | | | | This adds new image files which come with a DRAM FIFO. The addition of an N320 image with a DRAM FIFO allows DDR3 BIST to be run on an assembled (motherboard + daughterboard) N320. This image is intentionally very similar to the N300_AA and N310_AA targets which serve the same purpose of providing an image with a DRAM FIFO for their respective devices.
* fpga: lib: Add xge features for new xport_svAndrew Moch2020-07-311-100/+191
| | | | | | | | | | - Made some things optional to reduce logic when used with the new xport_sv: (1) Clocking to sys_clk (2) Preamble insertion - New options to CUTTHROUGH faster on the TX path. The new xport_sv already has a gate to accumulate at its clock crossing.
* fpga: sim: Update PkgEthernetAndrew Moch2020-07-311-57/+91
| | | | | | Consolidated calcuation of last_tkeep and tkeep_last. Changed error checking to support unwrinkling tkeep/trailing changes in 100G etherent and support for testing packet dropping on backup.
* fpga: sim: Fix AxiLiteBfmAndrew Moch2020-07-311-3/+3
| | | | | AxiLiteBfm incorrectly included stb argument on rd() and printed actual response instead of expected in debug message.
* fpga: lib: Update AxiLiteIfAndrew Moch2020-07-311-1/+74
| | | | | This fixes a bug on wrstb in AxiLiteIf and adds a new AxiLiteIf_v that can be used to stitch onto Verilog port_maps.
* fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64Andrew Moch2020-07-301-1/+1
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