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* fpga: n3xx: Fix DRAM FIFO address alignmentWade Fife2022-02-103-6/+6
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* fpga: rfnoc: Change AWIDTH default for axi_ram_fifoWade Fife2022-02-101-1/+1
| | | | | Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs assume the AXI address width is the same as MEM_ADDR_W.
* fpga: e31x: Add DRAM supportWade Fife2022-02-1015-99/+1499
| | | | | | | | | This adds DRAM support to E31x devices. Due to the size of the DDR3 memory controller, it is not enabled by default. You can include the memory controller IP in the build by adding the DRAM environment variable to your build. For example: DRAM=1 make E310_SG3
* fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parametersJonathon Pendlum2022-02-103-11/+20
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* fpga: x400: Add DRAM enable macroJavier Valenzuela2022-02-101-0/+4
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* images: Add utilization report files to B2xx image filesMartin Braun2022-02-101-4/+8
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* fpga: b2xx: Generate utilization report filesMartin Braun2022-02-102-18/+24
| | | | | | | | | | | | Currently, the build process copies the .twr and .syr files into the build/ process after running ISE. For a succinct utilization report, those files are not suitable, though, because they contain too much information. However, the build process already produces a custom, short utilization report using grep and a summary of those reports. This patch modifies the build such that the same output is copied into a usrp_$product_fpga.rpt file, similar to our gen-3 devices.
* fpga: x400: zbx: cpld: Bump ZBX regmap copyrightJavier Valenzuela2022-02-1011-11/+11
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* fpga: x400: cpld: Bump CMI wrapper copyrightJavier Valenzuela2022-02-102-2/+2
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* fpga: ci: Increase PR pipeline timeoutWade Fife2022-02-071-3/+3
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* fpga: x400: Bump minor versionWade Fife2022-02-073-8/+8
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* fpga: x400: Update rfnoc_image_core filesWade Fife2022-02-078-98/+1327
| | | | | Updates the RFNoC image core files to include DRAM and default image changes.
* fpga: x400: Add Replay to 100 and 200 MHz imagesWade Fife2022-02-072-36/+107
| | | | | This adds the RFNoC replay block to the defautl 100 and 200 MHz images for X410.
* fpga: x400: Add DRAM supportWade Fife2022-02-075-106/+1272
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* fpga: x400: Set DRAM speed to 2.0 GT/sWade Fife2022-02-071-26/+26
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* fpga: x400: Add axi_inter_4x64_512_bd IPWade Fife2022-02-073-0/+604
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* fpga: x400: Add axi_inter_2x128_512_bd IPWade Fife2022-02-073-0/+449
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* images: Update N32x CPLD manifestHumberto Jimenez2022-01-311-1/+1
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* fpga: docs: Add B205mini FPGA infoWade Fife2022-01-281-9/+11
| | | | | | - Add ISE WebPACK supported FPGAs - Add FPGA type for B205mini - Update product name and URL for Vivado
* fpga: n3xx: rh: cpld: Refactor CPLD build processHumberto Jimenez2022-01-256-24/+119
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* fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svhMartin Braun2022-01-256-1058/+1
| | | | | Both files are a UHD 3 remnant and potentially confusing for UHD 4 codebase readers.
* fpga: x400: cpld: Bump copyrightJavier Valenzuela2022-01-259-9/+9
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* fpga: x400: Bump copyrightJavier Valenzuela2022-01-2514-14/+14
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* fpga: x400: Expand PS GPIO port for DIO controlJavier Valenzuela2022-01-257-19/+58
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* fpga: x400: Add SPI bus support for GPIO portsJavier Valenzuela2022-01-259-60/+1338
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* fpga: x400: Add GPIO control via ATR and DB stateJavier Valenzuela2022-01-2514-199/+2932
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* fpga: x400: Connect Radio Blocks to DIOJavier Valenzuela2022-01-2511-232/+627
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* fpga: tools: Fix adding directories for HDL sourceWade Fife2022-01-131-1/+1
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* fpga: hls: Add version to generated HLS IPWade Fife2022-01-131-2/+2
| | | | | | | | | This change causes HLS IP to be exported with a version of 1.0.0 instead of a date code. Due to a bug in Vivado, date codes after 0x7FFFFFFF (anything in 2022 or beyond) cause an error. Setting an explicit revision avoids this issue. See Xilinx AR 76960 for details.
* fpga: x400: Fix rfnoc_image_core.vh pathWade Fife2022-01-121-1/+1
| | | | | | Previously, when running rfnoc_image_builder, the rfnoc_image_core.vh file in the main x400 directory was being used instead of the one generated by rfnoc_image_builder.
* uhd: update git://github.com references to httpsSteven Koo2022-01-113-13/+13
| | | | | | | GitHub is removing support for using git://. Switch to https. https://github.blog/2021-09-01-improving-git-protocol-security-github/ Signed-off-by: Steven Koo <steven.koo@ni.com>
* fpga: e320: Connect CTRL_IN pins to FPGAMartin Braun2022-01-102-1/+12
| | | | | | | | These pins control hardware-controlled fast-lock for tuning or cycle-accurate gain control. This commit does nothing to these pins other than expose them into the design and assign them to zero. This does not change the current behaviour (the motherboard has pull-downs on these pins, so they're low by default).
* fpga: e320: Remove copy/paste from N310 codeMartin Braun2022-01-101-9/+0
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* images: Add the utilization report for X410 images (X4_200)Martin Braun2021-12-171-1/+3
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* fpga: x300: Fix time register readbackWade Fife2021-12-151-2/+2
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* fpga: usrp2: update build tools to use python3Matthew Crymble2021-12-082-6/+6
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* fpga: tools: Update Vivado scripts to use python3Wade Fife2021-12-081-4/+4
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* rfnoc: Fix noc_shell direction commentsWade Fife2021-12-0818-81/+86
| | | | | | Some comments describing data flow direction were wrong. This commit updates the Mako files and updates the noc_shell modules with newly generated versions.
* fpga: x300: OR ATR signals going into db_controlMartin Braun2021-12-071-1/+10
| | | | | | | | | | | Before this change, only the channel 0 ATR state was sent to the db_control module. For TwinRX, this had the disadvantage that when only Channel 1 was used, the FP- and LED-GPIOs could not track the radio's ATR state (e.g., no LED would light up in this case). Note that unlike UHD 3, there is only one db_control module per slot. There are therefore no options to map GPIOs to track the ATR state of an individual channel.
* fpga: x400: cpld: Add manufacturing supportHumberto Jimenez2021-12-014-7/+27
| | | | | This commit enables a special personality on the X410 motherboard CPLD required for NI manufacturing purposes only.
* fpga: x400: Refactor CPLDs build processHumberto Jimenez2021-12-0134-258/+741
| | | | | | | | | | This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes.
* fpga: tools: Add Quartus build utilitiesHumberto Jimenez2021-12-013-0/+163
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* fpga: Add ability to get time from Radio blockmichael-west2021-11-173-2/+26
| | | | | | Added registers to read back radio time. Bumped minor compat. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: rfnoc: Add RFNoC CHDR resize moduleWade Fife2021-11-047-0/+2031
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* fpga: rfnoc: Add CHDR management util functionsWade Fife2021-11-041-4/+85
| | | | Add missing chdr_mgmt_*() and enum_to_chdr_w() functions.
* x410: correct 100GbE link speedAndrew Lynch2021-11-022-2/+2
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* fpga: lib: Clean up axi_muxWade Fife2021-10-281-91/+160
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* fpga: rfnoc: Add labels to axi_switch generate blocksWade Fife2021-10-281-36/+67
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* fpga: rfnoc: Add labels to chdr_mgmt_pkt_handlerWade Fife2021-10-281-30/+45
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* fpga: rfnoc: Add documentation to chdr_xb_routing_tableWade Fife2021-10-281-46/+84
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