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* fpga: e31x: Update constraints to avoid timing issuesWade Fife2020-04-081-6/+6
| | | | | | | Xilinx changed the way [all_registers -edge_triggered] is treated such that set_max_delay constraints that use it can cause segmentation and cause clocks to not be propagated to all endpoints. Changing to [all_ffs] avoids this potential issue.
* fpga: tools: Add support for .sdc in VivadoPaul Butler2020-04-021-0/+3
| | | | | | viv_utils.tcl will now read files with the .sdc suffix using the read_xdc Vivado command. This is especially useful when I/O timing constraints in the FPGA and CPLD need to depend on a common constant.
* fpga: rfnoc: Add gate to dynamically enable control-port interfacesMax Köhler2020-04-011-0/+91
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* fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1Max Köhler2020-04-011-13/+51
| | | | | The latency through the combiner is static if only one master interface is used and PRIORITY=1 is set.
* fpga: tools: Add default Vivado install locationWade Fife2020-04-011-1/+5
| | | | | | Xilinx changed the default Vivado install location from /opt/Xilix to /tools/Xilinx. This commit adds support for finding Vivado in either the new location or the old location.
* fpga: tools: Add ModelSim to run_testbenches.pyWade Fife2020-03-231-11/+11
| | | | | This adds the "modelsim" simulator option to run_testbenches.py to allow for regression testing of the native ModelSim simulation target.
* fixup! fpga: tools: Add modelsim to make sim targetsWade Fife2020-03-231-27/+25
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* fpga: Fix errors found by linting with vsimAndrew Moch2020-03-236-19/+22
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* fpga: tools: Add modelsim to make sim targetsAndrew Moch2020-03-204-35/+127
| | | | | | | | | | | | | | | This adds a simulation make target that allows you to run ModelSim natively rather than through Vivado. Adds or modifies the following simulation make targets: make vlint - Brake up compilation to Verilog/SystemVerilog/VHDL make modelsim - Depends on make vlint and invokes modelsim Adds the following variables: MODELSIM_ARGS - Added to invocation of ModelSim SVLOG_ARGS - Added to SystemVerilog invocation of vlog VLOG_ARGS - Added to Verilog invocation of vlog VHDL_ARGS - Added to VHDL invocation of vcom
* fpga: tools: Ignore BD layout info for TCL-based BDHumberto Jimenez2020-03-121-1/+1
| | | | | | | | | | | | | | | | | | When using viv_modify_tcl_bd, two Vivado instances are open: 1. GUI-mode Vivado that opens a TCL-based BD for the user to edit. 2. Batch-mode Vivado that saves changes from (1) and rewrites the TCL source file. During (2), the previous tool implementation was saving layout information in the TCL source file. This layout info gets outdated when the BD is reopened, because (1) regenerates the layout to provide a clean BD diagram in the Vivado GUI. Furthermore, each time the BD is open, the layout information will vary due to Vivado's window size, thus creating untracked changes in the source TCL file. This commit removes the command option that requests Vivado to save layout information.
* sim: Rename class typedefsWade Fife2020-03-094-72/+72
| | | | | | | | For example, the ChdrPacket typedef is being renamed from ChdrPacket to ChdrPacket_t. This allows the code to distinguish between the unparameterized class and the already parameterized class. This isn't strictly necessary, but it makes some Vivado 2019.1 bugs easier to work around. It also makes the code slightly less ambiguous.
* sim: Add ChdrIfaceBfm testWade Fife2020-03-095-5/+675
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* sim: Add item support to RFNoC simulationWade Fife2020-03-098-40/+420
| | | | | This adds variants of the send and recv methods in RfnocBlockCtrlBfm and ChdrIfaceBfm that input/output items instead of CHDR words.
* sim: Parameterize chdr_word_t data typeWade Fife2020-03-0916-216/+411
| | | | | | | | | | | | | | | | | | This replaces chdr_word_t, which was a statically defined 64-bit data type, with a paramaterizable data type that matches the defined CHDR_W. Code that formerly referenced the chdr_word_t data type can now define the data type for their desired CHDR_W and ITEM_W as follows: // Define the CHDR word and item/sample data types typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t; typedef ChdrData #(CHDR_W, ITEM_W)::item_t item_t; ITEM_W is optional when defining chdr_word_t if items are not needed. Static methods in the ChdrData class also provide the ability to convert between CHDR words and data items. For example: // Convert CHDR data buffer to a buffer of samples samples = ChdrData#(CHDR_W, ITEM_W)::chdr_to_item(data);
* sim: Split PkgRfnocBlockCtrlBfm into separate packagesWade Fife2020-03-095-400/+418
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* fpga: lib: Modify for loop to Verilog 2001 syntaxMax Köhler2020-03-091-34/+35
| | | | | | This changes the for loop to use the generate keyword, making it compatible with Verilog 2001. This allows tools that only support Verilog 2001 to use this file (e.g., Intel Quartus).
* rfnoc: Fix FIR and AXI RAM block register documentationWade Fife2020-03-052-9/+11
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* rfnoc: Add management filter to generic xportWade Fife2020-02-194-101/+172
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* radio: Update TB to use new block ctrl connectWade Fife2020-02-191-41/+17
| | | | | This eliminates the complicated semaphore from the testbench and brings the radio testbench in line with the other testbenches.
* x300: add front-panel GPIO source controleklai2020-02-182-7/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds a ZPU register to control the FP GPIO source. These are 2bits per GPIO pin, totalling 24 bits. 0 corresponds to RF-A, 1 corresponds to RF-B. The following Python code will control the upper 6 bits of the front-panel GPIO from the B-side radio on an X300: >>> import uhd >>> U = uhd.usrp.MultiUSRP("type=x300") >>> U.get_gpio_src_banks() ['FP0'] >>> U.get_gpio_src("FP0") ['RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA'] >>> U.set_gpio_src("FP0", ['RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFB', 'RFB', 'RFB', 'RFB', 'RFB', 'RFB']) >>> U.get_gpio_src("FP0") ['RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFB', 'RFB', 'RFB', 'RFB', 'RFB', 'RFB'] >>> # Make all GPIOs outputs: >>> U.set_gpio_attr("FP0A", "DDR", 0xFFF) >>> U.set_gpio_attr("FP0B", "DDR", 0xFFF) >>> # Control all GPIOs from software (not ATR): >>> U.set_gpio_attr("FP0A", "CTRL", 0x000) >>> U.set_gpio_attr("FP0B", "CTRL", 0x000) >>> # Bottom 3 pins go high from radio A >>> U.set_gpio_attr("FP0A", "OUT", 0x007) >>> # Top 3 pins go high from radio B >>> U.set_gpio_attr("FP0B", "OUT", 0xE00) Amends the gpio.cpp example to allow switching the source. Co-authored-by: Brent Stapleton <brent.stapleton@ettus.com>
* rfnoc: Update blocks to use autogenerated noc_shellWade Fife2020-02-0623-1825/+2407
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* fixup! lib: add option for output register in pps generatorHumberto Jimenez2020-02-051-1/+1
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* lib: add option for output register in pps generatorMax Köhler2020-01-281-2/+23
| | | | | | The pps_generator module receives a new parameter (PIPELINE) which can optionally add a register on the output. The default behaviour is unchanged.
* Merge FPGA repository back into UHD repositoryMartin Braun2020-01-283090-0/+2912909
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com>
* Removed copy of FPGA source files.Martin Braun2014-10-073343-3119114/+0
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* Merge branch 'maint'Martin Braun2014-09-24275-292796/+13460
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| * fpga: Multiple X300 FPGA bugfixes and enhancementsAshish Chaudhari2014-09-24275-292796/+13460
| | | | | | | | | | | | | | - Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300
* | fpga: Added FPGA code for B200 AD9361 host driver additionAshish Chaudhari2014-08-202-8/+19
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* fpga: Added FPGA code for X300 MIMO alignment bugfixAshish Chaudhari2014-08-195-50/+22
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* fpga: Updating FPGA code for UHD-3.7.2-rc1Ben Hilburn2014-07-2258-3128/+3153
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* fpga: updating b200 and x300 FPGA source code for latest imagesBen Hilburn2014-05-1471-4093/+117072
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* x300 fpga: updating FPGA code with latest bug fixesBen Hilburn2014-03-206-3411/+3432
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* Merge branch 'maint'Nicholas Corgan2014-03-1743-112988/+0
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| * fpga: removed superfluous B2x0 filesNicholas Corgan2014-02-2043-112988/+0
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* | Adding bootram.coe file from latest firmware changes.michael-west2014-03-031-2377/+2377
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* Pushing the bulk of UHD-3.7.0 code.Ben Hilburn2014-02-142194-1083/+1489296
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* b2xx: Updating FPGA source with recent bugfixes.Ben Hilburn2013-12-03103-626/+2019
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* Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.Ben Hilburn2013-10-10591-0/+292056
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* Merge branch 'fpga_master' into master_converter_workJosh Blum2013-08-285-13/+13
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* Merge branch 'fpga_master' into maintJosh Blum2013-05-092-4/+8
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* Merge branch 'fpga_master' into maintJosh Blum2013-04-021-0/+1
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* Merge branch 'fpga_master' into maintJosh Blum2013-03-259-43/+58
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* Merge branch 'fpga_master'Josh Blum2012-10-103-9/+28
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* Merge branch 'fpga_master'Josh Blum2012-10-053-6/+15
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* Merge branch 'b100_2rx_fpga' into b100_2rxJosh Blum2012-09-044-1/+134
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* Merge branch 'fpga_next' into nextJosh Blum2012-07-194-4/+4
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* Merge branch 'fpga_next' into nextJosh Blum2012-07-191-1/+8
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* Merge branch 'fpga_next' into nextJosh Blum2012-07-1713-724/+219
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* Merge branch 'master' into nextJosh Blum2012-07-163-43/+6
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| * Merge branch 'fpga_master'Josh Blum2012-07-163-43/+6
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