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* fpga: Add Switchboard RFNoC blockJesse Zhang2020-07-307-0/+1121
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* fpga, mpm: Bump FPGA compat numberRobertWalstab2020-07-243-3/+3
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* TwinRX: Fix increased noise floormichael-west2020-07-211-1/+1
| | | | | | - Fixed bus width from 25 to 24 bits Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: remove liberioRobertWalstab2020-07-204-127/+3
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* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-209-89/+68
| | | | | | This updates the makefiles for the testbenches so they can be run using "make modelsim" without any additional hacks. The "xsim" and "vsim" simulation targets also still work.
* fpga: e31x: Add gitignore fileMartin Braun2020-07-181-0/+8
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* e31x: Minor cleanup on top-level e31x.v moduleMartin Braun2020-07-182-15/+14
| | | | | | - Fixed some incorrect comments - Fixed some missing wire declarations for internal NIC - Fix wire declarations for GPIO (they were declared too late)
* e31x: Swap out liberio for internal ethernet in the idle imageRobertWalstab2020-07-181-2/+2
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* e31x: fpga: connect device_idRobertWalstab2020-07-181-1/+5
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* fpga: rfnoc: Add RFNoC Moving Average blockWade Fife2020-07-168-0/+1587
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* n32x: Swap out liberio for internal EthernetRobertWalstab2020-07-161-30/+138
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* n3xx: Swap out liberio for internal EthernetRobertWalstab2020-07-164-1115/+1262
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* e31x: Swap out liberio for internal EthernetRobertWalstab2020-07-165-429/+522
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* e320: Swap out liberio for internal EthernetAlex Williams2020-07-164-520/+532
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* fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntaxMax Köhler2020-07-101-39/+41
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* fpga: n3xx: Fix White Rabbit imagesWade Fife2020-07-011-3/+19
| | | | Unused CHDR port was not being drained of discovery packets.
* fpga: lib: Add width agnostic version of Ethernet InterfaceAndrew Moch2020-06-3014-0/+3340
| | | | | | | | | | | | | | | | | | The rnfoc/xport section is refactored in System Verilog to allow the following improvements (1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run at a different clock rate than the main ethernet pipe (2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run at a different clock rate than the main ethernet pipe (3) ENET_W - Sets the size of the eth_tx and eth_rx pipes. eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously against the original xport_sv implementation, and against the new implementation with widths of 64/128/512. A chdr_management node info request queries the port info of the node0 in the eth_interface. eth_ifc_synth_test.sv can be compiled with the make xsim target to test out the size of various configurations.
* fpga: rfnoc: Add Log-Power blockWade Fife2020-06-296-0/+1006
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* fpga: rfnoc: Fix chdr_update_length functionWade Fife2020-06-291-1/+1
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* fpga: rfnoc: Add RFNoC Window blockWade Fife2020-06-298-0/+1454
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* fpga: tools: Highlight suppressible errors from vlintWade Fife2020-06-291-1/+1
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* fpga: lib: Fix axi_packet_gate RAM dib widthWade Fife2020-06-291-1/+1
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* fpga: lib: Add features to axi_lite.vhAndrew Moch2020-06-261-23/+62
| | | | | | Contains a fix for the AXI4LITE_ASSIGN macro, and adds AXI4LITE_PORT_ASSIGN, AXI4LITE_PORT_ASSIGN_NR, and AXI4LITE_DEBUG_ASSIGN macros.
* fpga: lib: Add synthesizable AXI4-Stream SV componentsAndrew Moch2020-06-2520-78/+4195
| | | | | | | | | | | | | | | | | | | Components are connected together with AxiStreamIfc. Some features include: (1) Add bytes to the start of a packet (2) Remove bytes from a packet (3) Wrappers for some older components a. fifo - buffer but imediately pass a packet b. packet_gate - buffer and hold till end of packet c. width_conv - cross clock domains and change width of axi bus The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can be used to connect to ports with continuous assignment. AxiStreamPacketIf must be used procedurally but allows the following new methods: - reached_packet_byte - notify when tdata contains a paritcular byte - get_packet_byte/get_packet_field - extract a byte or field from axi - put_packet_byte/put_packet_field - overwrite a byte or field onto axi
* fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tbWade Fife2020-06-251-8/+16
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* fpga: lib: Add interface and model for AXI4-LiteAndrew Moch2020-06-246-1/+1099
| | | | | | | | | | | | | | | | | (1) Synthesizable AxiLiteIf (2) Simulation model for AxiLite contains an AxiLiteTransaction class and an AxiLiteBfm class. Important Methods a. wr - performs non-blocking write and checks for expected response b. wr_block - performs a blocking write and provides response c. rd - performs a non-blocking read and checks for expected response d. rd_block - persforms a blocking read and provides response The model allows parallel execution of reads and writes, but enforces rd and write ordering when using the above methods. When transactions are posted directly, ordering is not guaranteed, and reads and writes are put on the interface immediately.
* fpga: lib: Pipeline and add clken to ip_hdr_checksumAndrew Moch2020-06-244-66/+51
| | | | | | | Adds LATENCY parameter to control the ammount of pieplineing. Adds a clock enable to control the advance of the pipeline. Used in xport when calculating new UDP headers for CHDR traffic.
* fpga: tools: Fix ModelSim return statusWade Fife2020-06-182-5/+12
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* fpga: rfnoc: Add support for 512-bit CHDR widthsAndrew Moch2020-06-1819-389/+568
| | | | | | | | This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and chdr_stream_endpoint blocks so that wider CHDR widths are properly supported. It also updates PkgChdrBfm to able to properly test these blocks. The testbenches have been updated to test both 64 and 512-bit widths.
* fpga: lib: add extended spi core for 64bitMax Köhler2020-06-172-0/+287
| | | | | | | | | The existing SPI core (simple_spi_slave.v) was limited to 32 bit. This commit adds a second spi core with capability to transfer up to 64 bits while keeping the same amount of resources when using generic setting MAX_BITS = 32. Furthermore, the new module aligns mosi and miso with the edges of sclk. The register stages were not aligned in the existing version.
* fpga: tools: remove temporary Xilinx directories for BD recreationMax Köhler2020-06-151-10/+13
| | | | | | | During recreation of block diagrams any RTL modules will be kept in hidden directories within the build directory. Updates of the RTL sources might not be taken into account. Solution is to remove Xilinx's hidden project directories before calling vivado.
* fpga: Update RFNOC_EDGE_TBL_FILE for CygwinWade Fife2020-06-124-4/+4
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* fpga: tools: Allow multiple top modules with ModelSimWade Fife2020-06-111-1/+1
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* fpga: lib: extend wb_spi ability to limit transmission lengthMax Köhler2020-06-041-3/+9
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* fpga: lib: Fix writes in axil_regport_masterAndrew Moch2020-06-041-23/+43
| | | | | | | Previously, if a write occurred before the FIFO was ready then a write could hang as the data channel would complete but leave the address channel in a state where it would never complete. The fix is to hold off acknowledging on the data channel until the FIFO is ready.
* fpga: rfnoc: Add defaults for rate changingWade Fife2020-05-282-10/+14
| | | | | | Add DEFAULT_M and DEFAULT_N parameters for rate changing cores. This allows the host to not need to configure fixed rate change cores.
* fpga: tools: Improve detection of setupenv sourcingWade Fife2020-05-281-29/+31
| | | | | This change allows detection of attempting to execute setupenv.sh rather than sourcing it, which is required.
* fpga: rfnoc: Add RFNoC Add/Sub blockWade Fife2020-05-287-10/+1190
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* fpga: sim: Add packet_info_equal functionWade Fife2020-05-283-1/+15
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* rfnoc: Add Split Stream RFNoC blockWade Fife2020-05-286-0/+932
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* fpga: tools: Improve native ModelSim supportWade Fife2020-05-263-72/+255
| | | | | This adds support for colored output and support for directories added to the list of source files (for HLS support).
* fpga: tools: Add contents of directories for HDL sourceWade Fife2020-05-263-5/+26
| | | | | | | | For HLS builds, the output file names aren't known in advance. This makes it difficult to write the Makefile to pull in the files and pass them to the build tools. This change allows you to add a directory as your HDL source so that all files in the directory will be pulled in by the build process.
* fpga: rfnoc: Add Vector IIR RFNoC blockWade Fife2020-05-198-20/+1394
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* fpga: tools: Remove uhd_image_builderMartin Braun2020-05-184-1244/+0
| | | | | The image builder was replaced by rfnoc_image_builder, and has been obsolete since then.
* x300: Expand DRAM address space to 1GWade Fife2020-05-181-3/+3
| | | | | | The address ranges configured for the AXI interconnect IP limited the amount of accessible DRAM to two 32 MB regions. This change makes the full 1G available to all DRAM ports.
* fpga: e31x: Replace symbolic link for CygwinWade Fife2020-05-121-1/+1
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* fpga: tools: Fix HLS IP build with CygwinHumberto Jimenez2020-05-122-4/+10
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* fpga: rfnoc: Clean up ctrlport_splitter usageWade Fife2020-05-122-2/+2
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* fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1Wade Fife2020-05-121-45/+61
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* TwinRX: Remove decimation from frontendMichael West2020-05-121-36/+52
| | | | | | | | | | | | | | The decimation in the rx_frontend_gen3 was added to reduce the bandwidth between the Radio and the DDC due to the limitation in bandwidth over the crossbar for dynamically connected blocks. The default FPGA image for the X300 now has a static connection between the Radio and DDC, so this is no longer necessary. This change allows the TwinRX receive channels to be time aligned with channels from other daughterboards so they can be used in the same streamer. Signed-off-by: Michael West <michael.west@ettus.com>
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