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* rfnoc: Add Split Stream RFNoC blockWade Fife2020-05-286-0/+932
* fpga: tools: Improve native ModelSim supportWade Fife2020-05-263-72/+255
* fpga: tools: Add contents of directories for HDL sourceWade Fife2020-05-263-5/+26
* fpga: rfnoc: Add Vector IIR RFNoC blockWade Fife2020-05-198-20/+1394
* fpga: tools: Remove uhd_image_builderMartin Braun2020-05-184-1244/+0
* x300: Expand DRAM address space to 1GWade Fife2020-05-181-3/+3
* fpga: e31x: Replace symbolic link for CygwinWade Fife2020-05-121-1/+1
* fpga: tools: Fix HLS IP build with CygwinHumberto Jimenez2020-05-122-4/+10
* fpga: rfnoc: Clean up ctrlport_splitter usageWade Fife2020-05-122-2/+2
* fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1Wade Fife2020-05-121-45/+61
* TwinRX: Remove decimation from frontendMichael West2020-05-121-36/+52
* DUC/DDC: Add variable time incrementMichael West2020-05-125-19/+39
* X300: Make VITA time monotonicMichael West2020-05-121-2/+2
* fpga: Change default MTU to 10Wade Fife2020-05-115-5/+5
* fpga: sim: Don't affect packet arguments in chdr_to_axisWade Fife2020-05-041-4/+4
* fpga: sim: Fix get_slave_data_bfm methodWade Fife2020-05-041-1/+1
* fpga: sim: Export return types in PkgRfnocBlockCtrlBfmWade Fife2020-05-041-0/+2
* fpga: docs: Remove RFNoC targets from manualMartin Braun2020-04-301-28/+13
* rfnoc: Add RFNoC fosphor blockWade Fife2020-04-147-1/+1585
* fpga: rfnoc: Add option to sample sideband info at start of packetWade Fife2020-04-141-58/+117
* fpga: tools: Add -voptargs=+acc to ModelSim GUIWade Fife2020-04-141-1/+1
* fpga: core: Add chdr_update_length functionWade Fife2020-04-141-0/+21
* fpga: lib: Add AXI-Stream splitter (axis_split)Wade Fife2020-04-142-0/+129
* fpga: sim: Export ChdrPacket in PkgRfnoBlockCtrlBfmWade Fife2020-04-141-0/+1
* fpga: tools: Option to check for full Vivado versionHumberto Jimenez2020-04-141-0/+24
* fpga: e31x: Update constraints to avoid timing issuesWade Fife2020-04-081-6/+6
* fpga: tools: Add support for .sdc in VivadoPaul Butler2020-04-021-0/+3
* fpga: rfnoc: Add gate to dynamically enable control-port interfacesMax Köhler2020-04-011-0/+91
* fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1Max Köhler2020-04-011-13/+51
* fpga: tools: Add default Vivado install locationWade Fife2020-04-011-1/+5
* fpga: tools: Add ModelSim to run_testbenches.pyWade Fife2020-03-231-11/+11
* fixup! fpga: tools: Add modelsim to make sim targetsWade Fife2020-03-231-27/+25
* fpga: Fix errors found by linting with vsimAndrew Moch2020-03-236-19/+22
* fpga: tools: Add modelsim to make sim targetsAndrew Moch2020-03-204-35/+127
* fpga: tools: Ignore BD layout info for TCL-based BDHumberto Jimenez2020-03-121-1/+1
* sim: Rename class typedefsWade Fife2020-03-094-72/+72
* sim: Add ChdrIfaceBfm testWade Fife2020-03-095-5/+675
* sim: Add item support to RFNoC simulationWade Fife2020-03-098-40/+420
* sim: Parameterize chdr_word_t data typeWade Fife2020-03-0916-216/+411
* sim: Split PkgRfnocBlockCtrlBfm into separate packagesWade Fife2020-03-095-400/+418
* fpga: lib: Modify for loop to Verilog 2001 syntaxMax Köhler2020-03-091-34/+35
* rfnoc: Fix FIR and AXI RAM block register documentationWade Fife2020-03-052-9/+11
* rfnoc: Add management filter to generic xportWade Fife2020-02-194-101/+172
* radio: Update TB to use new block ctrl connectWade Fife2020-02-191-41/+17
* x300: add front-panel GPIO source controleklai2020-02-182-7/+45
* rfnoc: Update blocks to use autogenerated noc_shellWade Fife2020-02-0623-1825/+2407
* fixup! lib: add option for output register in pps generatorHumberto Jimenez2020-02-051-1/+1
* lib: add option for output register in pps generatorMax Köhler2020-01-281-2/+23
* Merge FPGA repository back into UHD repositoryMartin Braun2020-01-283090-0/+2912909
* Removed copy of FPGA source files.Martin Braun2014-10-073343-3119114/+0
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