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* fpga: tools: Fix part selection in setupenvSam O'Brien2021-06-101-4/+12
| | | | | | | | | | | | | | The script setupenv_base.sh, which is used to setup the development environmnet in the open source toolchain, adds some functions to the shell that are used to interact with vivado. Some of the functions were looking in the wrong argument for the product name. This commit fixes the bug. In addition, supplying an incorrect part name returned a rather opaque error message. This commit also fixes the error handling so that the intended error message is displayed. Signed-off-by: Sam O'Brien <sam.obrien@ni.com>
* fpga: Change RFNoC YAML version numbers to stringsWade Fife2021-06-0810-20/+20
| | | | | Change version from a numeric to a string, in order to differentiate between versions like "1.1" and "1.10".
* fpga: lib: Add modports to SV AXI-Stream blocksWade Fife2021-06-034-8/+8
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* fpga: lib: Add time_increment port to timekeeperWade Fife2021-06-031-17/+43
| | | | | Adds a time_increment port for situations in which the parameter TIME_INCREMENT can't be used. They offer the same behavior.
* fpga: lib: Pipeline ctrlport_timerWade Fife2021-06-031-24/+81
| | | | | | | This pipelines ctrlport_timer to eliminate the long combinational path caused by the time comparisons. This change also removes the PRECISION_BITS parameter and converts it to a signal named time_ignore_bits.
* fpga: lib: Add clock domain comments to interfacesWade Fife2021-06-037-13/+28
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* fpga: lib: Add 2 to 1 gearbox moduleWade Fife2021-06-035-0/+517
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* fpga: lib: Add PHASE parameter to sim_clk_genWade Fife2021-06-031-1/+3
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* fpga: lib: Add AXI4 (full) interfaceAndrew Moch2021-06-034-0/+619
| | | | | Add a SystemVerilog interface for connecting AXI4 ports, and an associated header file with helper macros.
* fpga: lib: add pause support to ethernet xportAndrew Moch2021-06-036-7/+112
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* fpga: lib: Add eth_ipv4_internalWade Fife2021-06-032-0/+442
| | | | | This adds a generic version of eth_internal that allows you to specify the CHDR width.
* fpga: lib: Add zynquplus family to axi_bitqHumberto Jimenez2021-06-031-12/+13
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* fpga: tools: Add ability to run commands before routeWade Fife2021-06-031-5/+11
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* fpga: tools: Add ability to patch IP during generationWade Fife2021-06-032-0/+87
| | | | | | This adds the ability to call BUILD_VIVADO_IP, as before, followed by REBUILD_VIVADO_IP_WITH_PATCH to patch a file generated by the IP and then rebuild the IP with the patched file.
* fpga: tools: Add support for RFSoCHumberto Jimenez2021-06-032-9/+9
| | | | | | | This commit includes the following changes to the tools: - Change part definition in XCI and BD editors for the RFSoC family - Resolve part name in Vivado IP management utilities with viv_gen_part_id.py
* fpga: lib: Minor cleanup of axi_lite.vhLars Amsel2021-06-031-2/+23
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* fpga: rfnoc: Add ability to disable output flow controlWade Fife2021-04-142-7/+22
| | | | | | | | | | | | | Per the RFNoC specification, if we set the frequency of flow control updates to 0 then the input stream will not send flow control status updates to the output stream handler. This change makes it so that when the frequency of flow control status updates is configured to be zero in the FPGA output stream handler (i.e., cfg_fc_freq_bytes and cfg_fc_freq_pkts are both 0 in chdr_stream_output) then the output stream handler will not use flow control. That is, chdr_stream_output will not expect stream status updates and will not restrict output packets.
* fpga: lib: Add rx_front_end_gen3 testbenchWade Fife2021-04-092-0/+247
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* fpga: lib: Update round_sd to eliminate X from simulationWade Fife2021-04-091-14/+45
| | | | | | | | | | | | The asynchronous feedback loop on the err signal causes X to get stuck on the sum signal when simulating. This change adds a check for simulation only to force X to 0 so that unknown inputs get resolved once the inputs are known. Also added default values to the ports out and strobe_out, since having them uninitialized and without reset was causing simulation issues in other modules. The FPGA will initialize them to 0, so this change makes the code equivalent to real hardware behavior.
* fpga: lib: Fix simulation of axi_fir_filterWade Fife2021-04-091-1/+1
| | | | | | The always(*) block was never executing in some simulators because there were no signals on the right-hand side in the block. Changing it to an initial block ensures it always runs.
* TwinRX: Remove frontend filtermichael-west2021-04-081-59/+8
| | | | | | | | | | Removing the FIR filter in the frontend to reclaim resources and remove redundancy when using a DDC block. The default image has a DDC block, so only users making custom RFNoC images and using TwinRX will need to take care to properly downconvert the full bandwidth coming from the radio block. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: docs: Improve documentation of rx_frontend_gen3Martin Braun2021-04-071-1/+73
| | | | Also fixes a typo in the calibration manual page.
* fpga: lib: Fix DDS_SIN_COS_LUT outputs in makefilePaul Butler2021-03-311-1/+1
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* fpga: dsp: Fix formatting of rx_dcoffset and add docsMartin Braun2021-03-091-38/+110
| | | | | - Adapt to coding guide - Add header that explains the module
* fpga: Remove Python2 support from build systemMartin Braun2021-01-0417-119/+121
| | | | | | | - 2to3 was used to convert the Python scripts, except where the tool choked and manual intervention was required - All references to "python" where replaced with "python3" - buffer() was replaced by memoryview()
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-114-358/+541
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* fpga: lib: add glitch free mux moduleMax Köhler2020-12-032-0/+30
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* fpga: e31x: Add OOT sources to Makefile.e31x.incWade Fife2020-11-131-0/+8
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* fpga: lib: Fix axis_strm_monitor parametersWade Fife2020-10-201-2/+2
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* fpga: lib: Fix small packets stuck in 10 GbE TXAndrew Moch2020-10-051-3/+17
| | | | | | Any packet less than CUT_THROUGH bytes has a high chance of getting stuck in the TX FIFO of the xge_mac_wrapper. In cut-through mode we were waiting for CUT_THROUGH bytes before transmitting the packet.
* fpga: lib: Fix 10 GbE cut-through modeAndrew Moch2020-09-161-4/+16
| | | | | | | When operating in cut-through mode the hold off from the MAC was not applying back pressure, so when the TX interface filled up, data was dropped. This bug was introduced when cut-through was added, and does not impact the original implementation.
* fpga: lib: add generic to disable bitq engine tri-statingMax Köhler2020-09-162-11/+16
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* fpga: docs: Update user manual for UHD 4.0Wade Fife2020-09-1111-542/+1042
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* fpga: e31x: Change image file to e310_rfnoc_image_coreWade Fife2020-09-093-5/+5
| | | | | | | This renames e31x_rfnoc_image_core.* to e310_rfnoc_image_core.*. This makes the naming consistent with the rest of the build process (which uses "e310" for all variants of e31x) and fixes an issue in which the wrong file name was used by rfnoc_image_builder.
* E320: Revert addition of Replay blockmichael-west2020-09-043-266/+270
| | | | | | The DMA FIFO is needed for DDR3 BIST, so it is being restored for now. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: Added AA image mappings to N320Aaron Rossetto2020-09-031-1/+6
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* fpga: Add Replay Block to RFNoC Core Imagemattprost2020-09-0320-591/+2586
| | | | | | | | Add the Replay RFNoC block to the RFNoC core image for x300, x310, n300, n310, n320/n321, and e320. The Replay block is contained within its own static connection, so previous default behavior is still supported. Signed-off-by: mattprost <matt.prost@ni.com>
* fpga: Update DRAM IO signaturesWade Fife2020-09-034-28/+28
| | | | | | | | This updates the IO signatures so that all devices and RFNoC blocks use the same IO signature for the DRAM. This is needed because the IO signatures must match between the RFNoC blocks and the devices. This means that some devices have extra bits in the IO signature for the address, but the extra bits will simply be ignored.
* fpga: sim: chdr_stream_endpoint_tb improvementsWade Fife2020-08-312-36/+150
| | | | | | | - Adds test coverage for stream command and status packets - Cleans up report output during simulation - Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can be run directly instead of just chdr_stream_endpoint_all_tb
* fpga: sim: Fix stream command and status modelsWade Fife2020-08-311-9/+9
| | | | | | | | This updates PkgChdrBfm to correct some errors when modeling stream command and stream status packets. - Fix behavior when CHDR_W = 512 - Fix assertions in read_ctrl()
* fpga: n3xx: Update AXI interconnect address rangeWade Fife2020-08-284-2928/+2217
| | | | | This change allows the entire 2 GiB address space to be accessed on each memory port.
* fpga: e320: Update AXI interconnect address rangeWade Fife2020-08-282-2195/+1373
| | | | | This change allows the entire 2 GiB address space to be accessed on each memory port.
* fpga: rfnoc: Update CHDR stream INIT commandWade Fife2020-08-281-3/+10
| | | | | | This changes the behavior of the stream command with the INIT OpCode such that sending the command with 0 for the values causes no flow control stream status packets to be sent in response to incoming data.
* fpga: lib: Fix lint warningsWade Fife2020-08-283-3/+3
| | | | | Fixes various synthesis/simulation warnings that were being generated due to incorrectly sized constants.
* fpga: rfnoc: Remove deprecated filesWade Fife2020-08-2323-2679/+5
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* fpga: Update coding guidelinesWade Fife2020-08-201-30/+107
| | | | | | | | | | - Update recommended header - Update module examples - Add file/naming guidelines for modules - Add default_nettype recommendation - Add guidelines for generate statements - Recommend all caps for constants - Misc typos and adjustments
* fpga: e31x: Change RFNoC Ctrl clock to 40 MHzWade Fife2020-08-192-1/+3
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* fpga: e320: Fix timeout for timekeeper registersWade Fife2020-08-191-191/+284
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: n3xx: Fix timeout for timekeeper registersWade Fife2020-08-193-195/+307
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: e31x: Fix timeout for timekeeper registersWade Fife2020-08-191-180/+278
| | | | | | | | Fixing an issue in which a very slow radio_clk (due to low sample clock rate) could cause bus transactions to be issued to the timekeeper faster than it could service them, resulting in a timeout. This change replaces RegPort with CtrlPort so that proper flow control can be maintained to the timekeeper.
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