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* fpga: e31x: Change RFNoC Ctrl clock to 40 MHzWade Fife2020-08-192-1/+3
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* fpga: e320: Fix timeout for timekeeper registersWade Fife2020-08-191-191/+284
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: n3xx: Fix timeout for timekeeper registersWade Fife2020-08-193-195/+307
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: e31x: Fix timeout for timekeeper registersWade Fife2020-08-191-180/+278
| | | | | | | | Fixing an issue in which a very slow radio_clk (due to low sample clock rate) could cause bus transactions to be issued to the timekeeper faster than it could service them, resulting in a timeout. This change replaces RegPort with CtrlPort so that proper flow control can be maintained to the timekeeper.
* fpga: lib: Add more CtrlPort constantsWade Fife2020-08-191-7/+12
| | | | Add some missing CtrlPort signal widths to ctrlport.vh.
* fpga: lib: Add ctrlport_to_regport bridgeWade Fife2020-08-192-0/+91
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* fpga: e320: Fix default YAML target to E320_1GMartin Braun2020-08-171-1/+1
| | | | | It was set to E320_HG, which is not a valid target, causing build errors unless -t E320_1G was provided to rfnoc_image_builder.
* fpga: e310: Fix device in image core YAMLWade Fife2020-08-141-1/+1
| | | | | Device was set to e31x, but this is not a valid device type. All e31x devices use the e310 device type.
* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
| | | | | This change prevents packets from being chopped midway if the switchboard configuration is changed when a packet is in flight.
* fpga: lib: Fix SWITCH_ON_LAST in axi_mux_selectWade Fife2020-08-131-18/+39
| | | | | Thange allows the mux to switch cleanly between packets, if the mux select input is changed while a packet is in flight.
* fpga: lib: add handshake to replace FIFO for ctrlport CDCMax Köhler2020-08-133-48/+143
| | | | | | | | The clock crossing of the ctrlport used FIFOs to transfer requests and responses between clock domains. This commit adds a handshake based on the pulse synchronizer to reduce the resource usage for ctrlport clock domain crossing. Data is stored in a single register while the pulse synchronizer handles the signaling of valid flags.
* n320: Double radio ingress buffer sizemattprost2020-08-122-8/+8
| | | | | | | This increases the size of the ingress buffers for the N320 radio to support 250MHz TX streaming rates. Signed-off-by: mattprost <matt.prost@ni.com>
* fpga: rfnoc: Fix clock crossing in axis_data_to_chdrWade Fife2020-08-121-69/+89
| | | | | | | | | This fixes some incorrectly handled clock crossings from axis_data_clk to axis_chdr_clk, which could have manifested as timing failures (on E320) or incorrect behavior, depending on the product and noc_shell configuration. Also cleans up trailing white space.
* fpga: lib: Change max FFT size to 1024Wade Fife2020-08-111-2/+2
| | | | | | | | | | | | | The max FFT size was 4096, but we don't currently have any devices that can do that without modification. This is because, currently, the FFT size must be the same as the packet size, and the largest packet size supported by most devices is about 8000 bytes, or 2000 sc16 samples. Therefore, the largest FFT size supported without modifying other code is 1024 samples. This change frees up about 21% of the LUTs and 36% of the BRAM used by axi_fft and makes the software block controller and the IP agree on the maximum FFT size.
* fpga: rfnoc: Add tests to FFT blockWade Fife2020-08-102-39/+202
| | | | | This adds additional tests to the testbench to cover register reads and basic IFFT functionaltiy.
* fpga: lib: add Intel MAX10 architecture for 2clk FIFOMax Köhler2020-08-062-28/+33
| | | | | | | | | | | | | This commit derives parameters for MAX10 devices if provided by the DEVICE parameter. MAX10 devices FIFO generator support up to 36 bit wide FIFOs using embedded memory (M9K) in simple dual port mode, which is treated equally to RAM in the parameters. In combination with sorting the ctrlport signals by usage, the used resources can be reduced on the MAX10 devices from 6 to 3 M9K blocks for a ctrlport_clk_cross instance without time and portids.
* fpga: lib: Update xport_svAndrew Moch2020-08-056-182/+437
| | | | | | | | | - Detect dropped words at the dispatch level. This prevents an overflow on CHDR from block CPU. - Dropped packets are recorded as CPU or CHDR drop count - Refactor to put chdr_xport_adapter.sv in different clock domain to improve timing - Unwrinkle tkeep/trailing transitions
* fpga: rfnoc: Add RFNoC Keep One in N blockAaron Rossetto2020-08-057-0/+1432
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* fpga: rfnoc: Add RFNoC Replay blockWade Fife2020-08-0411-875/+4101
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* fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ramWade Fife2020-08-041-0/+12
| | | | | Adding a check for bursts that cross the 4 KiB boundary to the AXI4 memory model. Crossing a 4 KiB boundary is not allowed by AXI4.
* fpga: rfnoc: Add support for CHDR_W < ITEM_W*NIPCWade Fife2020-08-042-137/+195
| | | | | | | | | This change fixes the case where CHDR_W < ITEM_W*NIPC. It also adds a state machine to stall the input to the pyld_fifo to ensure that the pkt_info_fifo will not overflow. Previously in some cases it allowed the same word to be inserted into the pyld_fifo multiple times.
* fpga: lib: Fix comments and indentation in axi_fifo_short.vWade Fife2020-08-041-98/+87
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* fpga: n320: Add BIST (AA) image filessteviez2020-07-315-0/+1148
| | | | | | | | | | This adds new image files which come with a DRAM FIFO. The addition of an N320 image with a DRAM FIFO allows DDR3 BIST to be run on an assembled (motherboard + daughterboard) N320. This image is intentionally very similar to the N300_AA and N310_AA targets which serve the same purpose of providing an image with a DRAM FIFO for their respective devices.
* fpga: lib: Add xge features for new xport_svAndrew Moch2020-07-311-100/+191
| | | | | | | | | | - Made some things optional to reduce logic when used with the new xport_sv: (1) Clocking to sys_clk (2) Preamble insertion - New options to CUTTHROUGH faster on the TX path. The new xport_sv already has a gate to accumulate at its clock crossing.
* fpga: sim: Update PkgEthernetAndrew Moch2020-07-311-57/+91
| | | | | | Consolidated calcuation of last_tkeep and tkeep_last. Changed error checking to support unwrinkling tkeep/trailing changes in 100G etherent and support for testing packet dropping on backup.
* fpga: sim: Fix AxiLiteBfmAndrew Moch2020-07-311-3/+3
| | | | | AxiLiteBfm incorrectly included stb argument on rd() and printed actual response instead of expected in debug message.
* fpga: lib: Update AxiLiteIfAndrew Moch2020-07-311-1/+74
| | | | | This fixes a bug on wrstb in AxiLiteIf and adds a new AxiLiteIf_v that can be used to stitch onto Verilog port_maps.
* fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64Andrew Moch2020-07-301-1/+1
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* fpga: tools: RESOLVE_PATH checks for an empty pathAndrew Moch2020-07-301-4/+4
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* fpga: rfnoc: Add Signal Generator RFNoC blockWade Fife2020-07-3012-18/+1925
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* fpga: lib: Add axis_packetize moduleWade Fife2020-07-302-0/+162
| | | | | | This module takes an AXI-Stream without TLAST and outputs the same AXI-Stream with TLAST based on the provided packet size input.
* fpga: Add Switchboard RFNoC blockJesse Zhang2020-07-307-0/+1121
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* fpga, mpm: Bump FPGA compat numberRobertWalstab2020-07-243-3/+3
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* TwinRX: Fix increased noise floormichael-west2020-07-211-1/+1
| | | | | | - Fixed bus width from 25 to 24 bits Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: remove liberioRobertWalstab2020-07-204-127/+3
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* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-209-89/+68
| | | | | | This updates the makefiles for the testbenches so they can be run using "make modelsim" without any additional hacks. The "xsim" and "vsim" simulation targets also still work.
* fpga: e31x: Add gitignore fileMartin Braun2020-07-181-0/+8
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* e31x: Minor cleanup on top-level e31x.v moduleMartin Braun2020-07-182-15/+14
| | | | | | - Fixed some incorrect comments - Fixed some missing wire declarations for internal NIC - Fix wire declarations for GPIO (they were declared too late)
* e31x: Swap out liberio for internal ethernet in the idle imageRobertWalstab2020-07-181-2/+2
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* e31x: fpga: connect device_idRobertWalstab2020-07-181-1/+5
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* fpga: rfnoc: Add RFNoC Moving Average blockWade Fife2020-07-168-0/+1587
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* n32x: Swap out liberio for internal EthernetRobertWalstab2020-07-161-30/+138
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* n3xx: Swap out liberio for internal EthernetRobertWalstab2020-07-164-1115/+1262
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* e31x: Swap out liberio for internal EthernetRobertWalstab2020-07-165-429/+522
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* e320: Swap out liberio for internal EthernetAlex Williams2020-07-164-520/+532
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* fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntaxMax Köhler2020-07-101-39/+41
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* fpga: n3xx: Fix White Rabbit imagesWade Fife2020-07-011-3/+19
| | | | Unused CHDR port was not being drained of discovery packets.
* fpga: lib: Add width agnostic version of Ethernet InterfaceAndrew Moch2020-06-3014-0/+3340
| | | | | | | | | | | | | | | | | | The rnfoc/xport section is refactored in System Verilog to allow the following improvements (1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run at a different clock rate than the main ethernet pipe (2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run at a different clock rate than the main ethernet pipe (3) ENET_W - Sets the size of the eth_tx and eth_rx pipes. eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously against the original xport_sv implementation, and against the new implementation with widths of 64/128/512. A chdr_management node info request queries the port info of the node0 in the eth_interface. eth_ifc_synth_test.sv can be compiled with the make xsim target to test out the size of various configurations.
* fpga: rfnoc: Add Log-Power blockWade Fife2020-06-296-0/+1006
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* fpga: rfnoc: Fix chdr_update_length functionWade Fife2020-06-291-1/+1
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