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* fpga: lib: add extended spi core for 64bitMax Köhler2020-06-172-0/+287
| | | | | | | | | The existing SPI core (simple_spi_slave.v) was limited to 32 bit. This commit adds a second spi core with capability to transfer up to 64 bits while keeping the same amount of resources when using generic setting MAX_BITS = 32. Furthermore, the new module aligns mosi and miso with the edges of sclk. The register stages were not aligned in the existing version.
* fpga: tools: remove temporary Xilinx directories for BD recreationMax Köhler2020-06-151-10/+13
| | | | | | | During recreation of block diagrams any RTL modules will be kept in hidden directories within the build directory. Updates of the RTL sources might not be taken into account. Solution is to remove Xilinx's hidden project directories before calling vivado.
* fpga: Update RFNOC_EDGE_TBL_FILE for CygwinWade Fife2020-06-124-4/+4
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* fpga: tools: Allow multiple top modules with ModelSimWade Fife2020-06-111-1/+1
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* fpga: lib: extend wb_spi ability to limit transmission lengthMax Köhler2020-06-041-3/+9
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* fpga: lib: Fix writes in axil_regport_masterAndrew Moch2020-06-041-23/+43
| | | | | | | Previously, if a write occurred before the FIFO was ready then a write could hang as the data channel would complete but leave the address channel in a state where it would never complete. The fix is to hold off acknowledging on the data channel until the FIFO is ready.
* fpga: rfnoc: Add defaults for rate changingWade Fife2020-05-282-10/+14
| | | | | | Add DEFAULT_M and DEFAULT_N parameters for rate changing cores. This allows the host to not need to configure fixed rate change cores.
* fpga: tools: Improve detection of setupenv sourcingWade Fife2020-05-281-29/+31
| | | | | This change allows detection of attempting to execute setupenv.sh rather than sourcing it, which is required.
* fpga: rfnoc: Add RFNoC Add/Sub blockWade Fife2020-05-287-10/+1190
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* fpga: sim: Add packet_info_equal functionWade Fife2020-05-283-1/+15
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* rfnoc: Add Split Stream RFNoC blockWade Fife2020-05-286-0/+932
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* fpga: tools: Improve native ModelSim supportWade Fife2020-05-263-72/+255
| | | | | This adds support for colored output and support for directories added to the list of source files (for HLS support).
* fpga: tools: Add contents of directories for HDL sourceWade Fife2020-05-263-5/+26
| | | | | | | | For HLS builds, the output file names aren't known in advance. This makes it difficult to write the Makefile to pull in the files and pass them to the build tools. This change allows you to add a directory as your HDL source so that all files in the directory will be pulled in by the build process.
* fpga: rfnoc: Add Vector IIR RFNoC blockWade Fife2020-05-198-20/+1394
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* fpga: tools: Remove uhd_image_builderMartin Braun2020-05-184-1244/+0
| | | | | The image builder was replaced by rfnoc_image_builder, and has been obsolete since then.
* x300: Expand DRAM address space to 1GWade Fife2020-05-181-3/+3
| | | | | | The address ranges configured for the AXI interconnect IP limited the amount of accessible DRAM to two 32 MB regions. This change makes the full 1G available to all DRAM ports.
* fpga: e31x: Replace symbolic link for CygwinWade Fife2020-05-121-1/+1
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* fpga: tools: Fix HLS IP build with CygwinHumberto Jimenez2020-05-122-4/+10
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* fpga: rfnoc: Clean up ctrlport_splitter usageWade Fife2020-05-122-2/+2
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* fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1Wade Fife2020-05-121-45/+61
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* TwinRX: Remove decimation from frontendMichael West2020-05-121-36/+52
| | | | | | | | | | | | | | The decimation in the rx_frontend_gen3 was added to reduce the bandwidth between the Radio and the DDC due to the limitation in bandwidth over the crossbar for dynamically connected blocks. The default FPGA image for the X300 now has a static connection between the Radio and DDC, so this is no longer necessary. This change allows the TwinRX receive channels to be time aligned with channels from other daughterboards so they can be used in the same streamer. Signed-off-by: Michael West <michael.west@ettus.com>
* DUC/DDC: Add variable time incrementMichael West2020-05-125-19/+39
| | | | | | | | | Sets time increment based on tick rate and sample rate instead of assuming one tick per sample. Defaults to legacy behavior. Minor compat number bumped on DUC and DDC blocks. Signed-off-by: Michael West <michael.west@ettus.com>
* X300: Make VITA time monotonicMichael West2020-05-121-2/+2
| | | | | | Make timekeeper tick on every cycle of the radio clock. Signed-off-by: Michael West <michael.west@ettus.com>
* fpga: Change default MTU to 10Wade Fife2020-05-115-5/+5
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* fpga: sim: Don't affect packet arguments in chdr_to_axisWade Fife2020-05-041-4/+4
| | | | | | | | This updates the chdr_to_axis method so that it doesn't change the input chdr_packet object. This is useful in case there are other references to that object in use. Not modifying the object means that you don't always have to copy the object before passing it to this method.
* fpga: sim: Fix get_slave_data_bfm methodWade Fife2020-05-041-1/+1
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* fpga: sim: Export return types in PkgRfnocBlockCtrlBfmWade Fife2020-05-041-0/+2
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* rfnoc: Add RFNoC fosphor blockWade Fife2020-04-147-1/+1585
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* fpga: rfnoc: Add option to sample sideband info at start of packetWade Fife2020-04-141-58/+117
| | | | | | | | The axis_data_to_chdr block previously only sampled the sideband information at the end of the packet. This adds a parameter that controls if the sideband information should be sampled at the beginning of the packet or the end of the packet. In the former case, large internal packet buffers are not required.
* fpga: tools: Add -voptargs=+acc to ModelSim GUIWade Fife2020-04-141-1/+1
| | | | | | Add -voptargs=+acc to the default options when running vsim. This option enables debug command access to objects in the design, which is generally needed for debugging in the GUI.
* fpga: core: Add chdr_update_length functionWade Fife2020-04-141-0/+21
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* fpga: lib: Add AXI-Stream splitter (axis_split)Wade Fife2020-04-142-0/+129
| | | | | | | The axis_split module takes a single AXI-Stream input and duplicates it onto multiple AXI-Stream outputs. This block correctly handles the somewhat tricky flow-control logic so that the AXI-Stream handshake protocol is honored at all top-level ports.
* fpga: sim: Export ChdrPacket in PkgRfnoBlockCtrlBfmWade Fife2020-04-141-0/+1
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* fpga: tools: Option to check for full Vivado versionHumberto Jimenez2020-04-141-0/+24
| | | | | | | | | | | | | | | | | | | | | | This commits enables the FPGA build infrastructure to require a very specific Vivado version, all the way to the patch level. Vivado typically has the following version format: Year.release.update_patch This commit enables setupenv_base.sh to optionally look for the environment variable VIVADO_VER_FULL, which should contain the full Vivado version in the format specified above. Vivado is directly used to retrieve the installed version, returning an error if the requested version is not found. Example in setupenv.sh (which calls setupenv_base.sh): VIVADO_VER=2019.1 VIVADO_VER_FULL=2019.1.1_AR73068 The setupenv.sh script will setup Vivado 2019.1, but it will also verify that both Update 1 and patch AR73068 are installed.
* fpga: e31x: Update constraints to avoid timing issuesWade Fife2020-04-081-6/+6
| | | | | | | Xilinx changed the way [all_registers -edge_triggered] is treated such that set_max_delay constraints that use it can cause segmentation and cause clocks to not be propagated to all endpoints. Changing to [all_ffs] avoids this potential issue.
* fpga: tools: Add support for .sdc in VivadoPaul Butler2020-04-021-0/+3
| | | | | | viv_utils.tcl will now read files with the .sdc suffix using the read_xdc Vivado command. This is especially useful when I/O timing constraints in the FPGA and CPLD need to depend on a common constant.
* fpga: rfnoc: Add gate to dynamically enable control-port interfacesMax Köhler2020-04-011-0/+91
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* fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1Max Köhler2020-04-011-13/+51
| | | | | The latency through the combiner is static if only one master interface is used and PRIORITY=1 is set.
* fpga: tools: Add default Vivado install locationWade Fife2020-04-011-1/+5
| | | | | | Xilinx changed the default Vivado install location from /opt/Xilix to /tools/Xilinx. This commit adds support for finding Vivado in either the new location or the old location.
* fpga: tools: Add ModelSim to run_testbenches.pyWade Fife2020-03-231-11/+11
| | | | | This adds the "modelsim" simulator option to run_testbenches.py to allow for regression testing of the native ModelSim simulation target.
* fixup! fpga: tools: Add modelsim to make sim targetsWade Fife2020-03-231-27/+25
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* fpga: Fix errors found by linting with vsimAndrew Moch2020-03-236-19/+22
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* fpga: tools: Add modelsim to make sim targetsAndrew Moch2020-03-203-33/+124
| | | | | | | | | | | | | | | This adds a simulation make target that allows you to run ModelSim natively rather than through Vivado. Adds or modifies the following simulation make targets: make vlint - Brake up compilation to Verilog/SystemVerilog/VHDL make modelsim - Depends on make vlint and invokes modelsim Adds the following variables: MODELSIM_ARGS - Added to invocation of ModelSim SVLOG_ARGS - Added to SystemVerilog invocation of vlog VLOG_ARGS - Added to Verilog invocation of vlog VHDL_ARGS - Added to VHDL invocation of vcom
* fpga: tools: Ignore BD layout info for TCL-based BDHumberto Jimenez2020-03-121-1/+1
| | | | | | | | | | | | | | | | | | When using viv_modify_tcl_bd, two Vivado instances are open: 1. GUI-mode Vivado that opens a TCL-based BD for the user to edit. 2. Batch-mode Vivado that saves changes from (1) and rewrites the TCL source file. During (2), the previous tool implementation was saving layout information in the TCL source file. This layout info gets outdated when the BD is reopened, because (1) regenerates the layout to provide a clean BD diagram in the Vivado GUI. Furthermore, each time the BD is open, the layout information will vary due to Vivado's window size, thus creating untracked changes in the source TCL file. This commit removes the command option that requests Vivado to save layout information.
* sim: Rename class typedefsWade Fife2020-03-094-72/+72
| | | | | | | | For example, the ChdrPacket typedef is being renamed from ChdrPacket to ChdrPacket_t. This allows the code to distinguish between the unparameterized class and the already parameterized class. This isn't strictly necessary, but it makes some Vivado 2019.1 bugs easier to work around. It also makes the code slightly less ambiguous.
* sim: Add ChdrIfaceBfm testWade Fife2020-03-095-5/+675
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* sim: Add item support to RFNoC simulationWade Fife2020-03-098-40/+420
| | | | | This adds variants of the send and recv methods in RfnocBlockCtrlBfm and ChdrIfaceBfm that input/output items instead of CHDR words.
* sim: Parameterize chdr_word_t data typeWade Fife2020-03-0916-216/+411
| | | | | | | | | | | | | | | | | | This replaces chdr_word_t, which was a statically defined 64-bit data type, with a paramaterizable data type that matches the defined CHDR_W. Code that formerly referenced the chdr_word_t data type can now define the data type for their desired CHDR_W and ITEM_W as follows: // Define the CHDR word and item/sample data types typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t; typedef ChdrData #(CHDR_W, ITEM_W)::item_t item_t; ITEM_W is optional when defining chdr_word_t if items are not needed. Static methods in the ChdrData class also provide the ability to convert between CHDR words and data items. For example: // Convert CHDR data buffer to a buffer of samples samples = ChdrData#(CHDR_W, ITEM_W)::chdr_to_item(data);
* sim: Split PkgRfnocBlockCtrlBfm into separate packagesWade Fife2020-03-095-400/+418
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* fpga: lib: Modify for loop to Verilog 2001 syntaxMax Köhler2020-03-091-34/+35
| | | | | | This changes the for loop to use the generate keyword, making it compatible with Verilog 2001. This allows tools that only support Verilog 2001 to use this file (e.g., Intel Quartus).
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