| Commit message (Expand) | Author | Age | Files | Lines |
* | n32x: Swap out liberio for internal Ethernet | RobertWalstab | 2020-07-16 | 1 | -30/+138 |
* | n3xx: Swap out liberio for internal Ethernet | RobertWalstab | 2020-07-16 | 4 | -1115/+1262 |
* | e31x: Swap out liberio for internal Ethernet | RobertWalstab | 2020-07-16 | 5 | -429/+522 |
* | e320: Swap out liberio for internal Ethernet | Alex Williams | 2020-07-16 | 4 | -520/+532 |
* | fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntax | Max Köhler | 2020-07-10 | 1 | -39/+41 |
* | fpga: n3xx: Fix White Rabbit images | Wade Fife | 2020-07-01 | 1 | -3/+19 |
* | fpga: lib: Add width agnostic version of Ethernet Interface | Andrew Moch | 2020-06-30 | 14 | -0/+3340 |
* | fpga: rfnoc: Add Log-Power block | Wade Fife | 2020-06-29 | 6 | -0/+1006 |
* | fpga: rfnoc: Fix chdr_update_length function | Wade Fife | 2020-06-29 | 1 | -1/+1 |
* | fpga: rfnoc: Add RFNoC Window block | Wade Fife | 2020-06-29 | 8 | -0/+1454 |
* | fpga: tools: Highlight suppressible errors from vlint | Wade Fife | 2020-06-29 | 1 | -1/+1 |
* | fpga: lib: Fix axi_packet_gate RAM dib width | Wade Fife | 2020-06-29 | 1 | -1/+1 |
* | fpga: lib: Add features to axi_lite.vh | Andrew Moch | 2020-06-26 | 1 | -23/+62 |
* | fpga: lib: Add synthesizable AXI4-Stream SV components | Andrew Moch | 2020-06-25 | 20 | -78/+4195 |
* | fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tb | Wade Fife | 2020-06-25 | 1 | -8/+16 |
* | fpga: lib: Add interface and model for AXI4-Lite | Andrew Moch | 2020-06-24 | 6 | -1/+1099 |
* | fpga: lib: Pipeline and add clken to ip_hdr_checksum | Andrew Moch | 2020-06-24 | 4 | -66/+51 |
* | fpga: tools: Fix ModelSim return status | Wade Fife | 2020-06-18 | 2 | -5/+12 |
* | fpga: rfnoc: Add support for 512-bit CHDR widths | Andrew Moch | 2020-06-18 | 19 | -389/+568 |
* | fpga: lib: add extended spi core for 64bit | Max Köhler | 2020-06-17 | 2 | -0/+287 |
* | fpga: tools: remove temporary Xilinx directories for BD recreation | Max Köhler | 2020-06-15 | 1 | -10/+13 |
* | fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin | Wade Fife | 2020-06-12 | 4 | -4/+4 |
* | fpga: tools: Allow multiple top modules with ModelSim | Wade Fife | 2020-06-11 | 1 | -1/+1 |
* | fpga: lib: extend wb_spi ability to limit transmission length | Max Köhler | 2020-06-04 | 1 | -3/+9 |
* | fpga: lib: Fix writes in axil_regport_master | Andrew Moch | 2020-06-04 | 1 | -23/+43 |
* | fpga: rfnoc: Add defaults for rate changing | Wade Fife | 2020-05-28 | 2 | -10/+14 |
* | fpga: tools: Improve detection of setupenv sourcing | Wade Fife | 2020-05-28 | 1 | -29/+31 |
* | fpga: rfnoc: Add RFNoC Add/Sub block | Wade Fife | 2020-05-28 | 7 | -10/+1190 |
* | fpga: sim: Add packet_info_equal function | Wade Fife | 2020-05-28 | 3 | -1/+15 |
* | rfnoc: Add Split Stream RFNoC block | Wade Fife | 2020-05-28 | 6 | -0/+932 |
* | fpga: tools: Improve native ModelSim support | Wade Fife | 2020-05-26 | 3 | -72/+255 |
* | fpga: tools: Add contents of directories for HDL source | Wade Fife | 2020-05-26 | 3 | -5/+26 |
* | fpga: rfnoc: Add Vector IIR RFNoC block | Wade Fife | 2020-05-19 | 8 | -20/+1394 |
* | fpga: tools: Remove uhd_image_builder | Martin Braun | 2020-05-18 | 4 | -1244/+0 |
* | x300: Expand DRAM address space to 1G | Wade Fife | 2020-05-18 | 1 | -3/+3 |
* | fpga: e31x: Replace symbolic link for Cygwin | Wade Fife | 2020-05-12 | 1 | -1/+1 |
* | fpga: tools: Fix HLS IP build with Cygwin | Humberto Jimenez | 2020-05-12 | 2 | -4/+10 |
* | fpga: rfnoc: Clean up ctrlport_splitter usage | Wade Fife | 2020-05-12 | 2 | -2/+2 |
* | fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1 | Wade Fife | 2020-05-12 | 1 | -45/+61 |
* | TwinRX: Remove decimation from frontend | Michael West | 2020-05-12 | 1 | -36/+52 |
* | DUC/DDC: Add variable time increment | Michael West | 2020-05-12 | 5 | -19/+39 |
* | X300: Make VITA time monotonic | Michael West | 2020-05-12 | 1 | -2/+2 |
* | fpga: Change default MTU to 10 | Wade Fife | 2020-05-11 | 5 | -5/+5 |
* | fpga: sim: Don't affect packet arguments in chdr_to_axis | Wade Fife | 2020-05-04 | 1 | -4/+4 |
* | fpga: sim: Fix get_slave_data_bfm method | Wade Fife | 2020-05-04 | 1 | -1/+1 |
* | fpga: sim: Export return types in PkgRfnocBlockCtrlBfm | Wade Fife | 2020-05-04 | 1 | -0/+2 |
* | rfnoc: Add RFNoC fosphor block | Wade Fife | 2020-04-14 | 7 | -1/+1585 |
* | fpga: rfnoc: Add option to sample sideband info at start of packet | Wade Fife | 2020-04-14 | 1 | -58/+117 |
* | fpga: tools: Add -voptargs=+acc to ModelSim GUI | Wade Fife | 2020-04-14 | 1 | -1/+1 |
* | fpga: core: Add chdr_update_length function | Wade Fife | 2020-04-14 | 1 | -0/+21 |