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* fpga: x400: Fix rfnoc_image_core.vh pathWade Fife2022-01-121-1/+1
| | | | | | Previously, when running rfnoc_image_builder, the rfnoc_image_core.vh file in the main x400 directory was being used instead of the one generated by rfnoc_image_builder.
* uhd: update git://github.com references to httpsSteven Koo2022-01-113-13/+13
| | | | | | | GitHub is removing support for using git://. Switch to https. https://github.blog/2021-09-01-improving-git-protocol-security-github/ Signed-off-by: Steven Koo <steven.koo@ni.com>
* fpga: e320: Connect CTRL_IN pins to FPGAMartin Braun2022-01-102-1/+12
| | | | | | | | These pins control hardware-controlled fast-lock for tuning or cycle-accurate gain control. This commit does nothing to these pins other than expose them into the design and assign them to zero. This does not change the current behaviour (the motherboard has pull-downs on these pins, so they're low by default).
* fpga: e320: Remove copy/paste from N310 codeMartin Braun2022-01-101-9/+0
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* images: Add the utilization report for X410 images (X4_200)Martin Braun2021-12-171-1/+3
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* fpga: x300: Fix time register readbackWade Fife2021-12-151-2/+2
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* fpga: tools: Update Vivado scripts to use python3Wade Fife2021-12-081-4/+4
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* rfnoc: Fix noc_shell direction commentsWade Fife2021-12-0818-81/+86
| | | | | | Some comments describing data flow direction were wrong. This commit updates the Mako files and updates the noc_shell modules with newly generated versions.
* fpga: x300: OR ATR signals going into db_controlMartin Braun2021-12-071-1/+10
| | | | | | | | | | | Before this change, only the channel 0 ATR state was sent to the db_control module. For TwinRX, this had the disadvantage that when only Channel 1 was used, the FP- and LED-GPIOs could not track the radio's ATR state (e.g., no LED would light up in this case). Note that unlike UHD 3, there is only one db_control module per slot. There are therefore no options to map GPIOs to track the ATR state of an individual channel.
* fpga: x400: cpld: Add manufacturing supportHumberto Jimenez2021-12-014-7/+27
| | | | | This commit enables a special personality on the X410 motherboard CPLD required for NI manufacturing purposes only.
* fpga: x400: Refactor CPLDs build processHumberto Jimenez2021-12-0134-258/+741
| | | | | | | | | | This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes.
* fpga: tools: Add Quartus build utilitiesHumberto Jimenez2021-12-013-0/+163
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* fpga: Add ability to get time from Radio blockmichael-west2021-11-173-2/+26
| | | | | | Added registers to read back radio time. Bumped minor compat. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: rfnoc: Add RFNoC CHDR resize moduleWade Fife2021-11-047-0/+2031
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* fpga: rfnoc: Add CHDR management util functionsWade Fife2021-11-041-4/+85
| | | | Add missing chdr_mgmt_*() and enum_to_chdr_w() functions.
* x410: correct 100GbE link speedAndrew Lynch2021-11-022-2/+2
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* fpga: lib: Clean up axi_muxWade Fife2021-10-281-91/+160
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* fpga: rfnoc: Add labels to axi_switch generate blocksWade Fife2021-10-281-36/+67
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* fpga: rfnoc: Add labels to chdr_mgmt_pkt_handlerWade Fife2021-10-281-30/+45
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* fpga: rfnoc: Add documentation to chdr_xb_routing_tableWade Fife2021-10-281-46/+84
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* fpga: Shorten line length for Launchpad linterAaron Rossetto2021-10-281-2/+4
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* siggen: Fix direction of rotationWade Fife2021-10-274-35/+44
| | | | | | | | | The I and Q were swapped in sine_tone, which caused confusion and made the rotation of REG_CARTESIAN clockwise by default. This effectively made the resulting frequency negative. This PR makes the I and Q order consistent with RFNoC and fixes the direction of rotation so that a positive value for REG_PHASE_INC (phase increment) results in a counter-clockwise rotation, which yields a positive frequency.
* fpga: x300: Update synchronizer constraintWade Fife2021-09-131-1/+1
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* fpga: n3xx: Update synchronizer constraintWade Fife2021-09-131-3/+2
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* fpga: lib: Update example constraint in synchronizerWade Fife2021-09-131-18/+40
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* fpga: Update help message for setupenv.shWade Fife2021-09-101-5/+7
| | | | | Updates the language in setupenv.sh --help to better reflect that there are many locations where Vivado is searched.
* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-09-088-16/+8
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* fpga: tools: Add UHD_FPGA_DIR definition to synthesisWade Fife2021-09-083-6/+11
| | | | | | | | | | | | | | | | | This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to the location of the UHD "fpga" directory. This allows you to include files in your out-of-tree modules relative to the FPGA directory. For example, you could include the library header file rfnoc_chdr_utils.vh using the following: `include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" Some simulators may not support `" outside of the context of a `define, in which case you can do the following: `define RFNOC_CHDR_UTILS_PATH \ `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" `include `RFNOC_CHDR_UTILS_PATH
* fpga: Set default part for sim in setupenv.shWade Fife2021-08-306-5/+24
| | | | | | | | | This sets the ARCH and PART_ID environment variables so that the selected part family is used for simulations by default. This can be overridden by changing them in the Makefile for the testbench if a testbench requires a specific part family. Prior to this change, the default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which required support for that part to be installed.
* x300: Fix sfpp_io_core tuser widthWade Fife2021-08-271-1/+1
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* fpga: Fix Xilinx bitfile parser for Python 3Martin Braun2021-08-241-31/+54
| | | | | | | | | The script was previously only Python 2 compatible. Python 2 support is now removed, so we don't maintain backwards compatibility with Python 2. This also fixes all linter warnings.
* sim: Update chdr_16sc_to_sc12 testbenchmichael-west2021-08-101-137/+159
| | | | | | | Modified to send 2 packets back to back at each packet size to test output during sequential input packets. Also fixed whitespace. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: Re-order error and data packetsmichael-west2021-08-101-2/+28
| | | | | | | Added delay to error packets so overrun error is back in-band. Avoids dropping good data packets in the case of an overrun. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: Fix sc16 to sc12 convertermichael-west2021-08-101-62/+80
| | | | | | | | | Re-wrote converter to remove clock cycle delay on i_tready when handling residual output and fixed improper handling of tlast during residual data processing. Resolves some USB overflow issues when using sc12 data type on B200 devices. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: rfnoc: Fix EOB loss in DUCWade Fife2021-08-087-218/+1858
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were some rare corner cases where the EOB could get lost in the DUC due to the dds_timed logic not always passing it through as it should. This resulted in an underflow error message at the end of transmission. This commit also fixes an issue where part of the last packet used a frequency shift of 0 instead of the requested frequency shift, and an issue where the first few samples of a burst used the wrong frequency shift value. Part of the fix includes adding a TUSER port to dds_sin_cos_lut_only. The TUSER port is built into the IP but was disabled. It is now enabled and set to 1 bit wide. This has a very small effect on resource usage and can be left unconnected when not needed. The dds_freq_tune block was shared by the DUC and DDC. To avoid affecting the DDC, a new version, dds_freq_tune_duc, is being added for the DUC to use that has the necessary fixes. The new dds_wrapper.v is a wrapper for the dds_sin_cos_lut_only IP. This IP has the undesirable behavior that new inputs must be provided to push previous outputs through the IP. This wrapper hides that complexity by adding some logic to ensure all data gets pushed through automatically. This logic uses the TUSER port on the IP. Finally, a testbench for dds_timed was added.
* fpga: sim: Add PkgComplex, PkgMath, and PkgRandomWade Fife2021-08-085-0/+546
| | | | | | | | | | | | PkgComplex adds functions for doing complex arithmetic in SystemVerilog simulation. PkgMath provides mathematical operations and constants that aren't built into SystemVerilog, such as a constant for pi and the function round(). PkgRandom adds randomization functions beyond what standard Verilog supports but that don't require any special licenses or simulators.
* fpga: lib: Clean up and document lib filesWade Fife2021-08-083-246/+411
| | | | Clean-up and document axi_tag_time, dds_freq_tune, and axi_sync.
* rfnoc: duc: Remove stale references to CORDICWade Fife2021-08-081-18/+15
| | | | | Updated some comments that still referenced the old CORDIC implementation, which is no longer used.
* N3xx: Fix White Rabbitmichael-west2021-08-041-0/+10
| | | | | | | Reconnect the signals from the White Rabbit module to the TDC in the FPGA. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: x400: Remove stale information in register mapHumberto Jimenez2021-07-283-9/+9
| | | | | | White Rabbit is not supported in X410, however the register map included an incorrect reference to this unsupported feature. This commit removes the WR reference from both the source and html files.
* fpga: x400: Fix x4xx_qsfp_wrapper testbenchWade Fife2021-06-221-0/+3
| | | | | Reorder dependencies so that sc_util_v1_0_vl_rfs.sv gets compiled first when using ModelSim.
* fpga: sim: Check for empty packet in clear_unused_bytesWade Fife2021-06-171-0/+4
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* x400: sim: Move testbenches to sim folderWade Fife2021-06-1713-0/+0
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* fpga: Update testbenches to work in ModelSimWade Fife2021-06-1711-136/+303
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* fpga: x400: Add makefiles for RF testbenchesWade Fife2021-06-177-3/+212
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* fpga: tools: Detect assertions in ModelSim simulationWade Fife2021-06-171-2/+22
| | | | | | | This change allows assertion errors/failures in ModelSim to be detected and causes ModelSim to return a non-zero value when such an assertion error occurs. This allows the return value of ModelSim to be used to determine whether or not the testbench passed.
* fpga: tools: Put SIM_SRCS at end of compile orderWade Fife2021-06-171-1/+1
| | | | | | VHDL depends on the compile order. This commit changes the order so that SIM_SRCS are compiled last with ModelSim to avoid issues with dependencies.
* fpga: tools: Support new FPGA types in viv_simulator.makWade Fife2021-06-171-2/+2
| | | | | | This updates the existing PART_NAME generation used in simulation makefiles to work with newer part families by calling viv_gen_part_id.py to generate the part name needed by Vivado.
* fpga: tools: Fix python2 reference in viv_ip_builder.makWade Fife2021-06-171-1/+1
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* fpga: tools: Add modelsim.excludesWade Fife2021-06-171-0/+18
| | | | | This is a list of testbenches that don't work with ModelSim and should be excluded when running run_testbenches.py.
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