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* fpga: x400: Add axi_inter_2x128_512_bd IPWade Fife2022-02-073-0/+449
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* images: Update N32x CPLD manifestHumberto Jimenez2022-01-311-1/+1
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* fpga: n3xx: rh: cpld: Refactor CPLD build processHumberto Jimenez2022-01-256-24/+119
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* fpga: x400: cpld: Bump copyrightJavier Valenzuela2022-01-259-9/+9
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* fpga: x400: Bump copyrightJavier Valenzuela2022-01-2514-14/+14
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* fpga: x400: Expand PS GPIO port for DIO controlJavier Valenzuela2022-01-257-19/+58
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* fpga: x400: Add SPI bus support for GPIO portsJavier Valenzuela2022-01-259-60/+1338
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* fpga: x400: Add GPIO control via ATR and DB stateJavier Valenzuela2022-01-2514-199/+2932
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* fpga: x400: Connect Radio Blocks to DIOJavier Valenzuela2022-01-2510-305/+626
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* fpga: x400: Fix rfnoc_image_core.vh pathWade Fife2022-01-121-1/+1
| | | | | | Previously, when running rfnoc_image_builder, the rfnoc_image_core.vh file in the main x400 directory was being used instead of the one generated by rfnoc_image_builder.
* fpga: e320: Connect CTRL_IN pins to FPGAMartin Braun2022-01-102-1/+12
| | | | | | | | These pins control hardware-controlled fast-lock for tuning or cycle-accurate gain control. This commit does nothing to these pins other than expose them into the design and assign them to zero. This does not change the current behaviour (the motherboard has pull-downs on these pins, so they're low by default).
* fpga: e320: Remove copy/paste from N310 codeMartin Braun2022-01-101-9/+0
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* fpga: x300: Fix time register readbackWade Fife2021-12-151-2/+2
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* fpga: x300: OR ATR signals going into db_controlMartin Braun2021-12-071-1/+10
| | | | | | | | | | | Before this change, only the channel 0 ATR state was sent to the db_control module. For TwinRX, this had the disadvantage that when only Channel 1 was used, the FP- and LED-GPIOs could not track the radio's ATR state (e.g., no LED would light up in this case). Note that unlike UHD 3, there is only one db_control module per slot. There are therefore no options to map GPIOs to track the ATR state of an individual channel.
* fpga: x400: cpld: Add manufacturing supportHumberto Jimenez2021-12-014-7/+27
| | | | | This commit enables a special personality on the X410 motherboard CPLD required for NI manufacturing purposes only.
* fpga: x400: Refactor CPLDs build processHumberto Jimenez2021-12-0133-254/+733
| | | | | | | | | | This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes.
* x410: correct 100GbE link speedAndrew Lynch2021-11-022-2/+2
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* fpga: Shorten line length for Launchpad linterAaron Rossetto2021-10-281-2/+4
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* fpga: x300: Update synchronizer constraintWade Fife2021-09-131-1/+1
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* fpga: n3xx: Update synchronizer constraintWade Fife2021-09-131-3/+2
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* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-09-081-2/+1
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* fpga: Set default part for sim in setupenv.shWade Fife2021-08-305-0/+20
| | | | | | | | | This sets the ARCH and PART_ID environment variables so that the selected part family is used for simulations by default. This can be overridden by changing them in the Makefile for the testbench if a testbench requires a specific part family. Prior to this change, the default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which required support for that part to be installed.
* x300: Fix sfpp_io_core tuser widthWade Fife2021-08-271-1/+1
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* N3xx: Fix White Rabbitmichael-west2021-08-041-0/+10
| | | | | | | Reconnect the signals from the White Rabbit module to the TDC in the FPGA. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: x400: Remove stale information in register mapHumberto Jimenez2021-07-283-9/+9
| | | | | | White Rabbit is not supported in X410, however the register map included an incorrect reference to this unsupported feature. This commit removes the WR reference from both the source and html files.
* fpga: x400: Fix x4xx_qsfp_wrapper testbenchWade Fife2021-06-221-0/+3
| | | | | Reorder dependencies so that sc_util_v1_0_vl_rfs.sv gets compiled first when using ModelSim.
* x400: sim: Move testbenches to sim folderWade Fife2021-06-1713-0/+0
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* fpga: Update testbenches to work in ModelSimWade Fife2021-06-178-89/+232
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* fpga: x400: Add makefiles for RF testbenchesWade Fife2021-06-176-0/+209
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* fpga: x400: zbx: Add support for ZBX CPLDJavier Valenzuela2021-06-1037-0/+17727
| | | | | | | Co-authored-by: Cherwa Vang <cherwa.vang@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com>
* fpga: x400: cpld: Add support for X410 motherboard CPLDMax Köhler2021-06-1042-0/+8377
| | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
* fpga: x400: Add support for X410 motherboard FPGAWade Fife2021-06-10204-0/+299632
| | | | | | | | | | | | | Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com>
* fpga: Update rfnoc_image_core for all targetsWade Fife2021-06-1018-5780/+6492
| | | | | | Update rfnoc_image_core.v to take into account the new image_core_name fields and version strings. Add new rfnoc_image_core.vh. Update YAML where needed.
* fpga: Change RFNoC YAML version numbers to stringsWade Fife2021-06-0810-20/+20
| | | | | Change version from a numeric to a string, in order to differentiate between versions like "1.1" and "1.10".
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-111-3/+2
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* fpga: e31x: Add OOT sources to Makefile.e31x.incWade Fife2020-11-131-0/+8
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* fpga: e31x: Change image file to e310_rfnoc_image_coreWade Fife2020-09-093-5/+5
| | | | | | | This renames e31x_rfnoc_image_core.* to e310_rfnoc_image_core.*. This makes the naming consistent with the rest of the build process (which uses "e310" for all variants of e31x) and fixes an issue in which the wrong file name was used by rfnoc_image_builder.
* E320: Revert addition of Replay blockmichael-west2020-09-043-266/+270
| | | | | | The DMA FIFO is needed for DDR3 BIST, so it is being restored for now. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: Add Replay Block to RFNoC Core Imagemattprost2020-09-0320-591/+2586
| | | | | | | | Add the Replay RFNoC block to the RFNoC core image for x300, x310, n300, n310, n320/n321, and e320. The Replay block is contained within its own static connection, so previous default behavior is still supported. Signed-off-by: mattprost <matt.prost@ni.com>
* fpga: Update DRAM IO signaturesWade Fife2020-09-034-28/+28
| | | | | | | | This updates the IO signatures so that all devices and RFNoC blocks use the same IO signature for the DRAM. This is needed because the IO signatures must match between the RFNoC blocks and the devices. This means that some devices have extra bits in the IO signature for the address, but the extra bits will simply be ignored.
* fpga: n3xx: Update AXI interconnect address rangeWade Fife2020-08-284-2928/+2217
| | | | | This change allows the entire 2 GiB address space to be accessed on each memory port.
* fpga: e320: Update AXI interconnect address rangeWade Fife2020-08-282-2195/+1373
| | | | | This change allows the entire 2 GiB address space to be accessed on each memory port.
* fpga: e31x: Change RFNoC Ctrl clock to 40 MHzWade Fife2020-08-192-1/+3
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* fpga: e320: Fix timeout for timekeeper registersWade Fife2020-08-191-191/+284
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: n3xx: Fix timeout for timekeeper registersWade Fife2020-08-193-195/+307
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: e31x: Fix timeout for timekeeper registersWade Fife2020-08-191-180/+278
| | | | | | | | Fixing an issue in which a very slow radio_clk (due to low sample clock rate) could cause bus transactions to be issued to the timekeeper faster than it could service them, resulting in a timeout. This change replaces RegPort with CtrlPort so that proper flow control can be maintained to the timekeeper.
* fpga: e320: Fix default YAML target to E320_1GMartin Braun2020-08-171-1/+1
| | | | | It was set to E320_HG, which is not a valid target, causing build errors unless -t E320_1G was provided to rfnoc_image_builder.
* fpga: e310: Fix device in image core YAMLWade Fife2020-08-141-1/+1
| | | | | Device was set to e31x, but this is not a valid device type. All e31x devices use the e310 device type.
* n320: Double radio ingress buffer sizemattprost2020-08-122-8/+8
| | | | | | | This increases the size of the ingress buffers for the N320 radio to support 250MHz TX streaming rates. Signed-off-by: mattprost <matt.prost@ni.com>
* fpga: n320: Add BIST (AA) image filessteviez2020-07-315-0/+1148
| | | | | | | | | | This adds new image files which come with a DRAM FIFO. The addition of an N320 image with a DRAM FIFO allows DDR3 BIST to be run on an assembled (motherboard + daughterboard) N320. This image is intentionally very similar to the N300_AA and N310_AA targets which serve the same purpose of providing an image with a DRAM FIFO for their respective devices.
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-01 19:21:06 +0000