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* fpga: rfnoc: Remove rfnoc_version from target YAMLWade Fife2022-06-1014-14/+0
| | | | | | This causes the latest RFNoC protocol version to be used by default and avoids the need to update YAML files every time the RFNoC protocol version gets bumped.
* fpga: x400: Increase replay SEP buffer sizesWade Fife2022-04-066-28/+28
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* fpga: x400: Add timed commands support for all radio ctrlport endpointsJavier Valenzuela2022-04-047-182/+104
| | | | | | | | | | | | | Extends timed command support to all endpoints addressable by the radio ctrlport interface. Previously supported endpoints: - Daughterboard GPIO interface - RFDC timing control Newly supported endpoints: - DIO ATR control - DIO SPI control - DIO Source control
* fpga: Update all RFNoC imagesWade Fife2022-03-3129-468/+508
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* rfnoc: Update device port names in image core YAMLWade Fife2022-03-3114-654/+767
| | | | | | Update USRP RFNoC iamge core YAML files to use the more consistent device port names. Clean up the formatting and make the files more consistent.
* fpga: n3xx: Add missing BIST image core headersWade Fife2022-03-296-45/+108
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* fpga: Use PROTOVER and CHDR_W from RFNoC image builderWade Fife2022-03-2913-27/+113
| | | | | | This updates all RFNoC devices so that they get the RFNoC protocol version and CHDR width in the same way, from the output generated by the RFNoC image builder.
* fpga: n3xx: Fix clock frequency commentsWade Fife2022-03-261-2/+2
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* fpga: e31x: Update DRAM IP simulationWade Fife2022-03-231-4/+22
| | | | | Update the simulation to use the renamed IP. Add ModelSim support.
* fpga: e31x: Fix DRAM traffic gen IP nameWade Fife2022-03-231-1/+1
| | | | | Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to IP_DDR3_16BIT_TG_SRCS to match the naming of other variables.
* fpga: x400: Add x410_400_128_rfnoc_image_coreWade Fife2022-03-145-3/+1613
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* fpga: x400: Cleanup FPGA MakefileWade Fife2022-03-041-40/+61
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* fpga: x400: Add support for DRAM with 400 MHz BWWade Fife2022-03-042-22/+24
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* fpga: x400: Change AXI XB for DRAM to 512-bitWade Fife2022-03-041-106/+17
| | | | | | Change the width of the crossbar in the AXI Interconnect IP from 256-bit to 512-bit to match the DRAM memory controller width and to give better performance.
* fpga: x400: Add SPI Controller Info registerJavier Valenzuela2022-03-046-11/+156
| | | | | | Include a register that contains SPI controller information. Currently, it only provides the number of slaves addressable by the SPI engine.
* fpga: x400: Adjust SPI engine strobes alignmentJavier Valenzuela2022-03-044-9/+14
| | | | | | Modify behavior of clock crossing between radio_clk and radio_clk_2x. This ensures strobe signals are always asserted for a single radio_clk_2x cycle and when radio_clk is low.
* fpga: x400: Set replay SEP buffers to twice MTUWade Fife2022-02-242-8/+8
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* Remove FSRU-related filesMartin Braun2022-02-221-1/+0
| | | | | | | The FSRU (aka EISCAT) was never supported in UHD 4.0. The FPGA repository never had the relevant files, and the block controller also never existed. This removes all the corresponding files from MPM, as well as some references from makefiles.
* fpga: e320: Add DRAM portsWade Fife2022-02-181-97/+97
| | | | | This adds two additional ports to the DRAM, for a total of up to four channels connected to DRAM.
* fpga: n3xx: Fix DRAM FIFO address alignmentWade Fife2022-02-103-6/+6
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* fpga: e31x: Add DRAM supportWade Fife2022-02-1015-99/+1499
| | | | | | | | | This adds DRAM support to E31x devices. Due to the size of the DDR3 memory controller, it is not enabled by default. You can include the memory controller IP in the build by adding the DRAM environment variable to your build. For example: DRAM=1 make E310_SG3
* fpga: x400: Add DRAM enable macroJavier Valenzuela2022-02-101-0/+4
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* fpga: b2xx: Generate utilization report filesMartin Braun2022-02-102-18/+24
| | | | | | | | | | | | Currently, the build process copies the .twr and .syr files into the build/ process after running ISE. For a succinct utilization report, those files are not suitable, though, because they contain too much information. However, the build process already produces a custom, short utilization report using grep and a summary of those reports. This patch modifies the build such that the same output is copied into a usrp_$product_fpga.rpt file, similar to our gen-3 devices.
* fpga: x400: zbx: cpld: Bump ZBX regmap copyrightJavier Valenzuela2022-02-1011-11/+11
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* fpga: x400: cpld: Bump CMI wrapper copyrightJavier Valenzuela2022-02-102-2/+2
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* fpga: x400: Bump minor versionWade Fife2022-02-073-8/+8
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* fpga: x400: Update rfnoc_image_core filesWade Fife2022-02-078-98/+1327
| | | | | Updates the RFNoC image core files to include DRAM and default image changes.
* fpga: x400: Add Replay to 100 and 200 MHz imagesWade Fife2022-02-072-36/+107
| | | | | This adds the RFNoC replay block to the defautl 100 and 200 MHz images for X410.
* fpga: x400: Add DRAM supportWade Fife2022-02-075-106/+1272
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* fpga: x400: Set DRAM speed to 2.0 GT/sWade Fife2022-02-071-26/+26
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* fpga: x400: Add axi_inter_4x64_512_bd IPWade Fife2022-02-073-0/+604
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* fpga: x400: Add axi_inter_2x128_512_bd IPWade Fife2022-02-073-0/+449
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* images: Update N32x CPLD manifestHumberto Jimenez2022-01-311-1/+1
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* fpga: n3xx: rh: cpld: Refactor CPLD build processHumberto Jimenez2022-01-256-24/+119
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* fpga: x400: cpld: Bump copyrightJavier Valenzuela2022-01-259-9/+9
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* fpga: x400: Bump copyrightJavier Valenzuela2022-01-2514-14/+14
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* fpga: x400: Expand PS GPIO port for DIO controlJavier Valenzuela2022-01-257-19/+58
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* fpga: x400: Add SPI bus support for GPIO portsJavier Valenzuela2022-01-259-60/+1338
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* fpga: x400: Add GPIO control via ATR and DB stateJavier Valenzuela2022-01-2514-199/+2932
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* fpga: x400: Connect Radio Blocks to DIOJavier Valenzuela2022-01-2510-305/+626
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* fpga: x400: Fix rfnoc_image_core.vh pathWade Fife2022-01-121-1/+1
| | | | | | Previously, when running rfnoc_image_builder, the rfnoc_image_core.vh file in the main x400 directory was being used instead of the one generated by rfnoc_image_builder.
* fpga: e320: Connect CTRL_IN pins to FPGAMartin Braun2022-01-102-1/+12
| | | | | | | | These pins control hardware-controlled fast-lock for tuning or cycle-accurate gain control. This commit does nothing to these pins other than expose them into the design and assign them to zero. This does not change the current behaviour (the motherboard has pull-downs on these pins, so they're low by default).
* fpga: e320: Remove copy/paste from N310 codeMartin Braun2022-01-101-9/+0
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* fpga: x300: Fix time register readbackWade Fife2021-12-151-2/+2
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* fpga: x300: OR ATR signals going into db_controlMartin Braun2021-12-071-1/+10
| | | | | | | | | | | Before this change, only the channel 0 ATR state was sent to the db_control module. For TwinRX, this had the disadvantage that when only Channel 1 was used, the FP- and LED-GPIOs could not track the radio's ATR state (e.g., no LED would light up in this case). Note that unlike UHD 3, there is only one db_control module per slot. There are therefore no options to map GPIOs to track the ATR state of an individual channel.
* fpga: x400: cpld: Add manufacturing supportHumberto Jimenez2021-12-014-7/+27
| | | | | This commit enables a special personality on the X410 motherboard CPLD required for NI manufacturing purposes only.
* fpga: x400: Refactor CPLDs build processHumberto Jimenez2021-12-0133-254/+733
| | | | | | | | | | This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes.
* x410: correct 100GbE link speedAndrew Lynch2021-11-022-2/+2
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* fpga: Shorten line length for Launchpad linterAaron Rossetto2021-10-281-2/+4
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* fpga: x300: Update synchronizer constraintWade Fife2021-09-131-1/+1
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