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* fpga: rfnoc: Remove rfnoc_version from target YAMLWade Fife2022-06-1014-14/+0
* fpga: x400: Increase replay SEP buffer sizesWade Fife2022-04-066-28/+28
* fpga: x400: Add timed commands support for all radio ctrlport endpointsJavier Valenzuela2022-04-047-182/+104
* fpga: Update all RFNoC imagesWade Fife2022-03-3129-468/+508
* rfnoc: Update device port names in image core YAMLWade Fife2022-03-3114-654/+767
* fpga: n3xx: Add missing BIST image core headersWade Fife2022-03-296-45/+108
* fpga: Use PROTOVER and CHDR_W from RFNoC image builderWade Fife2022-03-2913-27/+113
* fpga: n3xx: Fix clock frequency commentsWade Fife2022-03-261-2/+2
* fpga: e31x: Update DRAM IP simulationWade Fife2022-03-231-4/+22
* fpga: e31x: Fix DRAM traffic gen IP nameWade Fife2022-03-231-1/+1
* fpga: x400: Add x410_400_128_rfnoc_image_coreWade Fife2022-03-145-3/+1613
* fpga: x400: Cleanup FPGA MakefileWade Fife2022-03-041-40/+61
* fpga: x400: Add support for DRAM with 400 MHz BWWade Fife2022-03-042-22/+24
* fpga: x400: Change AXI XB for DRAM to 512-bitWade Fife2022-03-041-106/+17
* fpga: x400: Add SPI Controller Info registerJavier Valenzuela2022-03-046-11/+156
* fpga: x400: Adjust SPI engine strobes alignmentJavier Valenzuela2022-03-044-9/+14
* fpga: x400: Set replay SEP buffers to twice MTUWade Fife2022-02-242-8/+8
* Remove FSRU-related filesMartin Braun2022-02-221-1/+0
* fpga: e320: Add DRAM portsWade Fife2022-02-181-97/+97
* fpga: n3xx: Fix DRAM FIFO address alignmentWade Fife2022-02-103-6/+6
* fpga: e31x: Add DRAM supportWade Fife2022-02-1015-99/+1499
* fpga: x400: Add DRAM enable macroJavier Valenzuela2022-02-101-0/+4
* fpga: b2xx: Generate utilization report filesMartin Braun2022-02-102-18/+24
* fpga: x400: zbx: cpld: Bump ZBX regmap copyrightJavier Valenzuela2022-02-1011-11/+11
* fpga: x400: cpld: Bump CMI wrapper copyrightJavier Valenzuela2022-02-102-2/+2
* fpga: x400: Bump minor versionWade Fife2022-02-073-8/+8
* fpga: x400: Update rfnoc_image_core filesWade Fife2022-02-078-98/+1327
* fpga: x400: Add Replay to 100 and 200 MHz imagesWade Fife2022-02-072-36/+107
* fpga: x400: Add DRAM supportWade Fife2022-02-075-106/+1272
* fpga: x400: Set DRAM speed to 2.0 GT/sWade Fife2022-02-071-26/+26
* fpga: x400: Add axi_inter_4x64_512_bd IPWade Fife2022-02-073-0/+604
* fpga: x400: Add axi_inter_2x128_512_bd IPWade Fife2022-02-073-0/+449
* images: Update N32x CPLD manifestHumberto Jimenez2022-01-311-1/+1
* fpga: n3xx: rh: cpld: Refactor CPLD build processHumberto Jimenez2022-01-256-24/+119
* fpga: x400: cpld: Bump copyrightJavier Valenzuela2022-01-259-9/+9
* fpga: x400: Bump copyrightJavier Valenzuela2022-01-2514-14/+14
* fpga: x400: Expand PS GPIO port for DIO controlJavier Valenzuela2022-01-257-19/+58
* fpga: x400: Add SPI bus support for GPIO portsJavier Valenzuela2022-01-259-60/+1338
* fpga: x400: Add GPIO control via ATR and DB stateJavier Valenzuela2022-01-2514-199/+2932
* fpga: x400: Connect Radio Blocks to DIOJavier Valenzuela2022-01-2510-305/+626
* fpga: x400: Fix rfnoc_image_core.vh pathWade Fife2022-01-121-1/+1
* fpga: e320: Connect CTRL_IN pins to FPGAMartin Braun2022-01-102-1/+12
* fpga: e320: Remove copy/paste from N310 codeMartin Braun2022-01-101-9/+0
* fpga: x300: Fix time register readbackWade Fife2021-12-151-2/+2
* fpga: x300: OR ATR signals going into db_controlMartin Braun2021-12-071-1/+10
* fpga: x400: cpld: Add manufacturing supportHumberto Jimenez2021-12-014-7/+27
* fpga: x400: Refactor CPLDs build processHumberto Jimenez2021-12-0133-254/+733
* x410: correct 100GbE link speedAndrew Lynch2021-11-022-2/+2
* fpga: Shorten line length for Launchpad linterAaron Rossetto2021-10-281-2/+4
* fpga: x300: Update synchronizer constraintWade Fife2021-09-131-1/+1
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