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* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-111-3/+2
* fpga: e31x: Add OOT sources to Makefile.e31x.incWade Fife2020-11-131-0/+8
* fpga: e31x: Change image file to e310_rfnoc_image_coreWade Fife2020-09-093-5/+5
* E320: Revert addition of Replay blockmichael-west2020-09-043-266/+270
* fpga: Add Replay Block to RFNoC Core Imagemattprost2020-09-0320-591/+2586
* fpga: Update DRAM IO signaturesWade Fife2020-09-034-28/+28
* fpga: n3xx: Update AXI interconnect address rangeWade Fife2020-08-284-2928/+2217
* fpga: e320: Update AXI interconnect address rangeWade Fife2020-08-282-2195/+1373
* fpga: e31x: Change RFNoC Ctrl clock to 40 MHzWade Fife2020-08-192-1/+3
* fpga: e320: Fix timeout for timekeeper registersWade Fife2020-08-191-191/+284
* fpga: n3xx: Fix timeout for timekeeper registersWade Fife2020-08-193-195/+307
* fpga: e31x: Fix timeout for timekeeper registersWade Fife2020-08-191-180/+278
* fpga: e320: Fix default YAML target to E320_1GMartin Braun2020-08-171-1/+1
* fpga: e310: Fix device in image core YAMLWade Fife2020-08-141-1/+1
* n320: Double radio ingress buffer sizemattprost2020-08-122-8/+8
* fpga: n320: Add BIST (AA) image filessteviez2020-07-315-0/+1148
* fpga, mpm: Bump FPGA compat numberRobertWalstab2020-07-243-3/+3
* fpga: remove liberioRobertWalstab2020-07-201-1/+1
* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-201-3/+4
* fpga: e31x: Add gitignore fileMartin Braun2020-07-181-0/+8
* e31x: Minor cleanup on top-level e31x.v moduleMartin Braun2020-07-182-15/+14
* e31x: Swap out liberio for internal ethernet in the idle imageRobertWalstab2020-07-181-2/+2
* e31x: fpga: connect device_idRobertWalstab2020-07-181-1/+5
* n32x: Swap out liberio for internal EthernetRobertWalstab2020-07-161-30/+138
* n3xx: Swap out liberio for internal EthernetRobertWalstab2020-07-164-1115/+1262
* e31x: Swap out liberio for internal EthernetRobertWalstab2020-07-165-429/+522
* e320: Swap out liberio for internal EthernetAlex Williams2020-07-164-520/+532
* fpga: n3xx: Fix White Rabbit imagesWade Fife2020-07-011-3/+19
* fpga: Update RFNOC_EDGE_TBL_FILE for CygwinWade Fife2020-06-124-4/+4
* x300: Expand DRAM address space to 1GWade Fife2020-05-181-3/+3
* fpga: e31x: Replace symbolic link for CygwinWade Fife2020-05-121-1/+1
* X300: Make VITA time monotonicMichael West2020-05-121-2/+2
* fpga: e31x: Update constraints to avoid timing issuesWade Fife2020-04-081-6/+6
* rfnoc: Add management filter to generic xportWade Fife2020-02-191-30/+34
* x300: add front-panel GPIO source controleklai2020-02-182-7/+45
* Merge FPGA repository back into UHD repositoryMartin Braun2020-01-281088-0/+685426
* Removed copy of FPGA source files.Martin Braun2014-10-072073-1320378/+0
* Merge branch 'maint'Martin Braun2014-09-24269-292575/+13138
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| * fpga: Multiple X300 FPGA bugfixes and enhancementsAshish Chaudhari2014-09-24269-292575/+13138
* | fpga: Added FPGA code for B200 AD9361 host driver additionAshish Chaudhari2014-08-202-8/+19
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* fpga: Added FPGA code for X300 MIMO alignment bugfixAshish Chaudhari2014-08-195-50/+22
* fpga: Updating FPGA code for UHD-3.7.2-rc1Ben Hilburn2014-07-2254-3107/+3101
* fpga: updating b200 and x300 FPGA source code for latest imagesBen Hilburn2014-05-1465-3594/+116541
* x300 fpga: updating FPGA code with latest bug fixesBen Hilburn2014-03-206-3411/+3432
* Merge branch 'maint'Nicholas Corgan2014-03-1743-112988/+0
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| * fpga: removed superfluous B2x0 filesNicholas Corgan2014-02-2043-112988/+0
* | Adding bootram.coe file from latest firmware changes.michael-west2014-03-031-2377/+2377
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* Pushing the bulk of UHD-3.7.0 code.Ben Hilburn2014-02-141939-56/+1464866
* b2xx: Updating FPGA source with recent bugfixes.Ben Hilburn2013-12-0324-156/+447
* Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.Ben Hilburn2013-10-10329-0/+134757
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