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* N3xx: Fix White Rabbitmichael-west2021-08-041-0/+10
| | | | | | | Reconnect the signals from the White Rabbit module to the TDC in the FPGA. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: x400: Remove stale information in register mapHumberto Jimenez2021-07-283-9/+9
| | | | | | White Rabbit is not supported in X410, however the register map included an incorrect reference to this unsupported feature. This commit removes the WR reference from both the source and html files.
* fpga: x400: Fix x4xx_qsfp_wrapper testbenchWade Fife2021-06-221-0/+3
| | | | | Reorder dependencies so that sc_util_v1_0_vl_rfs.sv gets compiled first when using ModelSim.
* x400: sim: Move testbenches to sim folderWade Fife2021-06-1713-0/+0
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* fpga: Update testbenches to work in ModelSimWade Fife2021-06-178-89/+232
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* fpga: x400: Add makefiles for RF testbenchesWade Fife2021-06-176-0/+209
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* fpga: x400: zbx: Add support for ZBX CPLDJavier Valenzuela2021-06-1037-0/+17727
| | | | | | | Co-authored-by: Cherwa Vang <cherwa.vang@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com>
* fpga: x400: cpld: Add support for X410 motherboard CPLDMax Köhler2021-06-1042-0/+8377
| | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
* fpga: x400: Add support for X410 motherboard FPGAWade Fife2021-06-10204-0/+299632
| | | | | | | | | | | | | Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com>
* fpga: Update rfnoc_image_core for all targetsWade Fife2021-06-1018-5780/+6492
| | | | | | Update rfnoc_image_core.v to take into account the new image_core_name fields and version strings. Add new rfnoc_image_core.vh. Update YAML where needed.
* fpga: Change RFNoC YAML version numbers to stringsWade Fife2021-06-0810-20/+20
| | | | | Change version from a numeric to a string, in order to differentiate between versions like "1.1" and "1.10".
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-111-3/+2
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* fpga: e31x: Add OOT sources to Makefile.e31x.incWade Fife2020-11-131-0/+8
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* fpga: e31x: Change image file to e310_rfnoc_image_coreWade Fife2020-09-093-5/+5
| | | | | | | This renames e31x_rfnoc_image_core.* to e310_rfnoc_image_core.*. This makes the naming consistent with the rest of the build process (which uses "e310" for all variants of e31x) and fixes an issue in which the wrong file name was used by rfnoc_image_builder.
* E320: Revert addition of Replay blockmichael-west2020-09-043-266/+270
| | | | | | The DMA FIFO is needed for DDR3 BIST, so it is being restored for now. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: Add Replay Block to RFNoC Core Imagemattprost2020-09-0320-591/+2586
| | | | | | | | Add the Replay RFNoC block to the RFNoC core image for x300, x310, n300, n310, n320/n321, and e320. The Replay block is contained within its own static connection, so previous default behavior is still supported. Signed-off-by: mattprost <matt.prost@ni.com>
* fpga: Update DRAM IO signaturesWade Fife2020-09-034-28/+28
| | | | | | | | This updates the IO signatures so that all devices and RFNoC blocks use the same IO signature for the DRAM. This is needed because the IO signatures must match between the RFNoC blocks and the devices. This means that some devices have extra bits in the IO signature for the address, but the extra bits will simply be ignored.
* fpga: n3xx: Update AXI interconnect address rangeWade Fife2020-08-284-2928/+2217
| | | | | This change allows the entire 2 GiB address space to be accessed on each memory port.
* fpga: e320: Update AXI interconnect address rangeWade Fife2020-08-282-2195/+1373
| | | | | This change allows the entire 2 GiB address space to be accessed on each memory port.
* fpga: e31x: Change RFNoC Ctrl clock to 40 MHzWade Fife2020-08-192-1/+3
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* fpga: e320: Fix timeout for timekeeper registersWade Fife2020-08-191-191/+284
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: n3xx: Fix timeout for timekeeper registersWade Fife2020-08-193-195/+307
| | | | | | This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem.
* fpga: e31x: Fix timeout for timekeeper registersWade Fife2020-08-191-180/+278
| | | | | | | | Fixing an issue in which a very slow radio_clk (due to low sample clock rate) could cause bus transactions to be issued to the timekeeper faster than it could service them, resulting in a timeout. This change replaces RegPort with CtrlPort so that proper flow control can be maintained to the timekeeper.
* fpga: e320: Fix default YAML target to E320_1GMartin Braun2020-08-171-1/+1
| | | | | It was set to E320_HG, which is not a valid target, causing build errors unless -t E320_1G was provided to rfnoc_image_builder.
* fpga: e310: Fix device in image core YAMLWade Fife2020-08-141-1/+1
| | | | | Device was set to e31x, but this is not a valid device type. All e31x devices use the e310 device type.
* n320: Double radio ingress buffer sizemattprost2020-08-122-8/+8
| | | | | | | This increases the size of the ingress buffers for the N320 radio to support 250MHz TX streaming rates. Signed-off-by: mattprost <matt.prost@ni.com>
* fpga: n320: Add BIST (AA) image filessteviez2020-07-315-0/+1148
| | | | | | | | | | This adds new image files which come with a DRAM FIFO. The addition of an N320 image with a DRAM FIFO allows DDR3 BIST to be run on an assembled (motherboard + daughterboard) N320. This image is intentionally very similar to the N300_AA and N310_AA targets which serve the same purpose of providing an image with a DRAM FIFO for their respective devices.
* fpga, mpm: Bump FPGA compat numberRobertWalstab2020-07-243-3/+3
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* fpga: remove liberioRobertWalstab2020-07-201-1/+1
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* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-201-3/+4
| | | | | | This updates the makefiles for the testbenches so they can be run using "make modelsim" without any additional hacks. The "xsim" and "vsim" simulation targets also still work.
* fpga: e31x: Add gitignore fileMartin Braun2020-07-181-0/+8
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* e31x: Minor cleanup on top-level e31x.v moduleMartin Braun2020-07-182-15/+14
| | | | | | - Fixed some incorrect comments - Fixed some missing wire declarations for internal NIC - Fix wire declarations for GPIO (they were declared too late)
* e31x: Swap out liberio for internal ethernet in the idle imageRobertWalstab2020-07-181-2/+2
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* e31x: fpga: connect device_idRobertWalstab2020-07-181-1/+5
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* n32x: Swap out liberio for internal EthernetRobertWalstab2020-07-161-30/+138
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* n3xx: Swap out liberio for internal EthernetRobertWalstab2020-07-164-1115/+1262
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* e31x: Swap out liberio for internal EthernetRobertWalstab2020-07-165-429/+522
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* e320: Swap out liberio for internal EthernetAlex Williams2020-07-164-520/+532
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* fpga: n3xx: Fix White Rabbit imagesWade Fife2020-07-011-3/+19
| | | | Unused CHDR port was not being drained of discovery packets.
* fpga: Update RFNOC_EDGE_TBL_FILE for CygwinWade Fife2020-06-124-4/+4
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* x300: Expand DRAM address space to 1GWade Fife2020-05-181-3/+3
| | | | | | The address ranges configured for the AXI interconnect IP limited the amount of accessible DRAM to two 32 MB regions. This change makes the full 1G available to all DRAM ports.
* fpga: e31x: Replace symbolic link for CygwinWade Fife2020-05-121-1/+1
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* X300: Make VITA time monotonicMichael West2020-05-121-2/+2
| | | | | | Make timekeeper tick on every cycle of the radio clock. Signed-off-by: Michael West <michael.west@ettus.com>
* fpga: e31x: Update constraints to avoid timing issuesWade Fife2020-04-081-6/+6
| | | | | | | Xilinx changed the way [all_registers -edge_triggered] is treated such that set_max_delay constraints that use it can cause segmentation and cause clocks to not be propagated to all endpoints. Changing to [all_ffs] avoids this potential issue.
* rfnoc: Add management filter to generic xportWade Fife2020-02-191-30/+34
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* x300: add front-panel GPIO source controleklai2020-02-182-7/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds a ZPU register to control the FP GPIO source. These are 2bits per GPIO pin, totalling 24 bits. 0 corresponds to RF-A, 1 corresponds to RF-B. The following Python code will control the upper 6 bits of the front-panel GPIO from the B-side radio on an X300: >>> import uhd >>> U = uhd.usrp.MultiUSRP("type=x300") >>> U.get_gpio_src_banks() ['FP0'] >>> U.get_gpio_src("FP0") ['RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA'] >>> U.set_gpio_src("FP0", ['RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFB', 'RFB', 'RFB', 'RFB', 'RFB', 'RFB']) >>> U.get_gpio_src("FP0") ['RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFA', 'RFB', 'RFB', 'RFB', 'RFB', 'RFB', 'RFB'] >>> # Make all GPIOs outputs: >>> U.set_gpio_attr("FP0A", "DDR", 0xFFF) >>> U.set_gpio_attr("FP0B", "DDR", 0xFFF) >>> # Control all GPIOs from software (not ATR): >>> U.set_gpio_attr("FP0A", "CTRL", 0x000) >>> U.set_gpio_attr("FP0B", "CTRL", 0x000) >>> # Bottom 3 pins go high from radio A >>> U.set_gpio_attr("FP0A", "OUT", 0x007) >>> # Top 3 pins go high from radio B >>> U.set_gpio_attr("FP0B", "OUT", 0xE00) Amends the gpio.cpp example to allow switching the source. Co-authored-by: Brent Stapleton <brent.stapleton@ettus.com>
* Merge FPGA repository back into UHD repositoryMartin Braun2020-01-281088-0/+685426
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com>
* Removed copy of FPGA source files.Martin Braun2014-10-072073-1320378/+0
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* Merge branch 'maint'Martin Braun2014-09-24269-292575/+13138
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| * fpga: Multiple X300 FPGA bugfixes and enhancementsAshish Chaudhari2014-09-24269-292575/+13138
| | | | | | | | | | | | | | - Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300
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