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* x300: Fix sfpp_io_core tuser widthWade Fife2021-08-271-1/+1
* N3xx: Fix White Rabbitmichael-west2021-08-041-0/+10
* fpga: x400: Remove stale information in register mapHumberto Jimenez2021-07-283-9/+9
* fpga: x400: Fix x4xx_qsfp_wrapper testbenchWade Fife2021-06-221-0/+3
* x400: sim: Move testbenches to sim folderWade Fife2021-06-1713-0/+0
* fpga: Update testbenches to work in ModelSimWade Fife2021-06-178-89/+232
* fpga: x400: Add makefiles for RF testbenchesWade Fife2021-06-176-0/+209
* fpga: x400: zbx: Add support for ZBX CPLDJavier Valenzuela2021-06-1037-0/+17727
* fpga: x400: cpld: Add support for X410 motherboard CPLDMax Köhler2021-06-1042-0/+8377
* fpga: x400: Add support for X410 motherboard FPGAWade Fife2021-06-10204-0/+299632
* fpga: Update rfnoc_image_core for all targetsWade Fife2021-06-1018-5780/+6492
* fpga: Change RFNoC YAML version numbers to stringsWade Fife2021-06-0810-20/+20
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-111-3/+2
* fpga: e31x: Add OOT sources to Makefile.e31x.incWade Fife2020-11-131-0/+8
* fpga: e31x: Change image file to e310_rfnoc_image_coreWade Fife2020-09-093-5/+5
* E320: Revert addition of Replay blockmichael-west2020-09-043-266/+270
* fpga: Add Replay Block to RFNoC Core Imagemattprost2020-09-0320-591/+2586
* fpga: Update DRAM IO signaturesWade Fife2020-09-034-28/+28
* fpga: n3xx: Update AXI interconnect address rangeWade Fife2020-08-284-2928/+2217
* fpga: e320: Update AXI interconnect address rangeWade Fife2020-08-282-2195/+1373
* fpga: e31x: Change RFNoC Ctrl clock to 40 MHzWade Fife2020-08-192-1/+3
* fpga: e320: Fix timeout for timekeeper registersWade Fife2020-08-191-191/+284
* fpga: n3xx: Fix timeout for timekeeper registersWade Fife2020-08-193-195/+307
* fpga: e31x: Fix timeout for timekeeper registersWade Fife2020-08-191-180/+278
* fpga: e320: Fix default YAML target to E320_1GMartin Braun2020-08-171-1/+1
* fpga: e310: Fix device in image core YAMLWade Fife2020-08-141-1/+1
* n320: Double radio ingress buffer sizemattprost2020-08-122-8/+8
* fpga: n320: Add BIST (AA) image filessteviez2020-07-315-0/+1148
* fpga, mpm: Bump FPGA compat numberRobertWalstab2020-07-243-3/+3
* fpga: remove liberioRobertWalstab2020-07-201-1/+1
* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-201-3/+4
* fpga: e31x: Add gitignore fileMartin Braun2020-07-181-0/+8
* e31x: Minor cleanup on top-level e31x.v moduleMartin Braun2020-07-182-15/+14
* e31x: Swap out liberio for internal ethernet in the idle imageRobertWalstab2020-07-181-2/+2
* e31x: fpga: connect device_idRobertWalstab2020-07-181-1/+5
* n32x: Swap out liberio for internal EthernetRobertWalstab2020-07-161-30/+138
* n3xx: Swap out liberio for internal EthernetRobertWalstab2020-07-164-1115/+1262
* e31x: Swap out liberio for internal EthernetRobertWalstab2020-07-165-429/+522
* e320: Swap out liberio for internal EthernetAlex Williams2020-07-164-520/+532
* fpga: n3xx: Fix White Rabbit imagesWade Fife2020-07-011-3/+19
* fpga: Update RFNOC_EDGE_TBL_FILE for CygwinWade Fife2020-06-124-4/+4
* x300: Expand DRAM address space to 1GWade Fife2020-05-181-3/+3
* fpga: e31x: Replace symbolic link for CygwinWade Fife2020-05-121-1/+1
* X300: Make VITA time monotonicMichael West2020-05-121-2/+2
* fpga: e31x: Update constraints to avoid timing issuesWade Fife2020-04-081-6/+6
* rfnoc: Add management filter to generic xportWade Fife2020-02-191-30/+34
* x300: add front-panel GPIO source controleklai2020-02-182-7/+45
* Merge FPGA repository back into UHD repositoryMartin Braun2020-01-281088-0/+685426
* Removed copy of FPGA source files.Martin Braun2014-10-072073-1320378/+0
* Merge branch 'maint'Martin Braun2014-09-24269-292575/+13138
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